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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dcb22f737sm8995633f8f.24.2025.02.10.02.44.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 02:44:37 -0800 (PST) Message-ID: Date: Mon, 10 Feb 2025 11:44:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] hw/net: cadence_gem: feat: add logic for the DISABLE_MASK bit in type2_compare_x_word_1 To: Peter Maydell , "Edgar E. Iglesias" Cc: "Andrew.Yuan" , alistair@alistair23.me, jasowang@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20241219061658.805-1-andrew.yuan@jaguarmicro.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/2/25 15:37, Peter Maydell wrote: > On Thu, 30 Jan 2025 at 22:31, Edgar E. Iglesias > wrote: >> On Mon, Jan 27, 2025 at 8:40 AM Peter Maydell wrote: >>> On Thu, 19 Dec 2024 at 06:17, Andrew.Yuan wrote: >>>> - rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; >>>> - mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); >>>> - compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); >>>> + disable_mask = >>>> + FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, DISABLE_MASK); >>>> + if (disable_mask) { >>>> + /* >>>> + * If disable_mask is set, >>>> + * mask_value is used as an additional 2 byte Compare Value. >>>> + * To simple, set mask = 0xFFFFFFFF, if disable_mask is set. >>>> + */ >>>> + rx_cmp = ldl_le_p(rxbuf_ptr + offset); >>>> + mask = 0xFFFFFFFF; >>>> + compare = cr0; >>>> + } else { >>>> + rx_cmp = lduw_le_p(rxbuf_ptr + offset); >>> >>> Is the change in behaviour in the !disable_mask codepath here >>> intentional? Previously we use one byte from rxbuf_ptr[offset], >>> duplicated into both halves of rx_cmp; now we will load two >>> different bytes from rxbuf_ptr[offset] and rxbuf_ptr[offset + 1]. >>> >>> If this is intended, we should say so in the commit message. >>> >> >> I agree that it should be mentioned (looks like a correct bugfix). > > Thanks. I've expanded the commit message: > > hw/net/cadence_gem: Fix the mask/compare/disable-mask logic > > Our current handling of the mask/compare logic in the Cadence > GEM ethernet device is wrong: > (1) we load the same byte twice from rx_buf when > creating the compare value > (2) we ignore the DISABLE_MASK flag > > The "Cadence IP for Gigabit Ethernet MAC Part Number: IP7014 IP Rev: > R1p12 - Doc Rev: 1.3 User Guide" states that if the DISABLE_MASK bit > in type2_compare_x_word_1 is set, the mask_value field in > type2_compare_x_word_0 is used as an additional 2 byte Compare Value. > > Correct these bugs: > * in the !disable_mask codepath, use lduw_le_p() so we > correctly load a 16-bit value for comparison > * in the disable_mask codepath, we load a full 4-byte value > from rx_buf for the comparison, set the compare value to > the whole of the cr0 register (i.e. the concatenation of > the mask and compare fields), and set mask to 0xffffffff > to force a 32-bit comparison > > and also tweaked the comment a bit: > > + /* > + * If disable_mask is set, mask_value is used as an > + * additional 2 byte Compare Value; that is equivalent > + * to using the whole cr0 register as the comparison value. > + * Load 32 bits of data from rx_buf, and set mask to > + * all-ones so we compare all 32 bits. > + */ > > and applied this to target-arm.next. > >> Other than that this patch looks good to me! > > Can I call that a Reviewed-by (with the above changes)? Reviewed-by: Philippe Mathieu-Daudé