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[189.47.46.41]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74eb9f8b984sm10516158b3a.150.2025.07.14.06.35.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Jul 2025 06:35:59 -0700 (PDT) Message-ID: Date: Mon, 14 Jul 2025 10:36:49 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 4/6] target/arm: Add FEAT_TCR2 To: Richard Henderson , Pierrick Bouvier , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org References: <20250711140828.1714666-1-gustavo.romero@linaro.org> <20250711140828.1714666-5-gustavo.romero@linaro.org> <21bfbfaa-f0df-413d-bad6-b69688ac381a@linaro.org> <65e20340-e164-4424-bc60-52d78b9a17b8@linaro.org> Content-Language: en-US From: Gustavo Romero In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, On 7/14/25 09:58, Richard Henderson wrote: > On 7/14/25 00:21, Pierrick Bouvier wrote: >> On 7/13/25 2:59 PM, Richard Henderson wrote: >>> On 7/11/25 08:08, Gustavo Romero wrote: >>>> Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers. >>>> These registers are extensions of the TCR_ELx registers and provide >>>> top-level control of the EL10 and EL20 translation regimes. >>>> >>>> Since the bits in these registers depend on other CPU features, and only >>>> FEAT_MEC is supported at the moment, the FEAT_TCR2 only implements the >>>> AMEC bits for now. >>>> >>>> Signed-off-by: Gustavo Romero >>> This causes a regression in tests/functional/test_aarch64_device_passthrough.py, by >>> continually trapping on an access to TCR2_EL1 while the HCRX_EL2 enable bit is not set. >>> >>> Unlike the similar SCTRL2 failure, it's not 100% clear to me how the guest and nested >>> guest kernels are related.  But it is clear that the outer kernel does not does not >>> support TCR2_EL1 (and also doesn't manipulate ID_AA64MMFR3_EL1 to hide FEAT_TCR2), but the >>> nested guest kernel does support TCR2_EL1. >>> >> >> The same kernel is used for host and guest. >> Maybe it's related to kvm support? > > Oops, no, the patch fails to enable HCRX_TCR2EN in hcrx_write or SCR_TCR2EN in scr_write. > The same is true for the previous patch with HCRX_SCTLR2EN and SCR_SCTLR2EN. Thanks for the investigation. I'm just taking a look at it right now. I'll send a v8 fixing it. Cheers, Gustavo