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([2a01:e35:2fb0:49e0:98dc:fe2:8fe8:bc3b]) by smtp.gmail.com with ESMTPSA id w17sm3634631wmk.12.2020.12.29.06.09.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Dec 2020 06:09:16 -0800 (PST) Subject: Re: Bug in Bonito? (mips/fuloong2e) To: Jiaxun Yang References: <771a6cd4-90a7-662e-5a5b-e8a9395a875@eik.bme.hu> <511225e2-f074-4318-4fb0-f695ca6befe0@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 29 Dec 2020 15:09:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-1.07, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Wu Zhangjin , "Michael S. Tsirkin" , Huacai Chen , qemu-devel@nongnu.org, Guenter Roeck Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/29/20 2:02 PM, Jiaxun Yang wrote: > 在 2020/12/29 18:47, Philippe Mathieu-Daudé 写道: >> On 12/29/20 6:26 AM, Jiaxun Yang wrote: >>> 在 2020/12/29 上午11:26, BALATON Zoltan 写道: >>>> Hello, >>>> >>>> While continuing with part two of my vt82c686b clean ups I've tried to >>>> implement SMBus IO base configuration in the vt82c686b-pm part that >>>> I've already done for vt8231 for pegasos2 and it should be the same >>>> for 686B. (In short, writing address to pm config 0x90 sets base >>>> address of smbus regs and bit 0 of 0xd2 enables/disables it.) This is >>>> what the firmware does first and it would allow removing hard coded >>>> 0xeee1 value and the property to set it and then I could reuse the >>>> same PM part in VT8231. >>>> >>> [...] >>>> Any idea what this is trying to do and how to fix it? >>> It's trying to translate Bonito style PCI config space r/w to >>> standard PCI >>> config space R/W. >>> >>> A quick galance told me change BONITO_PCICONF_REG_MASK to 0xff >>> may help. >> Per the datasheet section "5.7.5. Accessing PCI configuration space" >> 0xfc is the correct value, but the register number starts at the 2nd >> bit. So this is not a write access to register 0xd2 but 0x34? > > It seems like Loongson changed defination of the register? Maybe, I only have the bonito64 specs, not the Loongson2 ones. I am a bit confused, I thought the Fuloong 2E was based on bonito64 (which QEMU models). Do you know if the Loongson2 specs are public? > There is no shifting in kernel[1] as well. > > ``` > /* Type 1 configuration for offboard PCI bus */ > addr = (busnum << 16) | (device << 11) | (function << 8) | reg; > ``` OK, this makes sense after looking at Linux kernel commit e2fee5723bbd ("MIPS: Bonito64: Make Loongson independent from Bonito64 code.") [2] I'm a bit reluctant to modify hw/pci-host/bonito.c to make Loongson2 works without having the specs handy, justifying simply because "Linux uses it that way". OTOH it is pointless to maintain a model that has no users (thinking about not breaking the bonito64 model). [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e2fee5723bbd > > Thanks. > > [1]: > https://elixir.bootlin.com/linux/latest/source/arch/mips/pci/ops-loongson2.c > > > - Jiaxun >> >> If you can test, this is the snippet I plan to send later: >> >> -- >8 -- >> diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c >> index a99eced0657..65953766dd0 100644 >> --- a/hw/pci-host/bonito.c >> +++ b/hw/pci-host/bonito.c >> @@ -189,3 +189,3 @@ FIELD(BONGENCFG, PCIQUEUE,      12, 1) >>   #define BONITO_PCICONF_REG_MASK        0xFC >> -#define BONITO_PCICONF_REG_OFFSET      0 >> +#define BONITO_PCICONF_REG_OFFSET      2 >> --- >> >>> Thanks. >>> >>> - Jiaxun >>> >>>> Regards, >>>> BALATON Zoltan >>> > >