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([2400:4050:a840:1e00:9ac7:6d57:2b16:6932]) by smtp.gmail.com with ESMTPSA id n39-20020a056a000d6700b006e57defe737sm137165pfv.76.2024.02.28.18.27.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Feb 2024 18:28:00 -0800 (PST) Message-ID: Date: Thu, 29 Feb 2024 11:27:55 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 03/15] pcie_sriov: Reset SR-IOV extended capability To: Sriram Yagnaraman , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Alex Williamson , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini , =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Jason Wang , Keith Busch , Klaus Jensen , Markus Armbruster Cc: "qemu-devel@nongnu.org" , "qemu-block@nongnu.org" References: <20240228-reuse-v8-0-282660281e60@daynix.com> <20240228-reuse-v8-3-282660281e60@daynix.com> Content-Language: en-US From: Akihiko Odaki In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=2607:f8b0:4864:20::136; envelope-from=akihiko.odaki@daynix.com; helo=mail-il1-x136.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2024/02/29 1:23, Sriram Yagnaraman wrote: > > >> -----Original Message----- >> From: Akihiko Odaki >> Sent: Wednesday, 28 February 2024 12:33 >> To: Philippe Mathieu-Daudé ; Michael S. Tsirkin >> ; Marcel Apfelbaum ; >> Alex Williamson ; Cédric Le Goater >> ; Paolo Bonzini ; Daniel P. >> Berrangé ; Eduardo Habkost >> ; Sriram Yagnaraman >> ; Jason Wang ; >> Keith Busch ; Klaus Jensen ; Markus >> Armbruster >> Cc: qemu-devel@nongnu.org; qemu-block@nongnu.org; Akihiko Odaki >> >> Subject: [PATCH v8 03/15] pcie_sriov: Reset SR-IOV extended capability >> >> pcie_sriov_pf_disable_vfs() is called when resetting the PF, but it only disables >> VFs and does not reset SR-IOV extended capability, leaking the state and >> making the VF Enable register inconsistent with the actual state. >> >> Replace pcie_sriov_pf_disable_vfs() with pcie_sriov_pf_reset(), which does >> not only disable VFs but also resets the capability. >> >> Signed-off-by: Akihiko Odaki >> --- >> include/hw/pci/pcie_sriov.h | 4 ++-- >> hw/net/igb.c | 2 +- >> hw/nvme/ctrl.c | 2 +- >> hw/pci/pcie_sriov.c | 26 ++++++++++++++++++-------- >> 4 files changed, 22 insertions(+), 12 deletions(-) >> >> diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h index >> 095fb0c9edf9..b77eb7bf58ac 100644 >> --- a/include/hw/pci/pcie_sriov.h >> +++ b/include/hw/pci/pcie_sriov.h >> @@ -58,8 +58,8 @@ void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, >> uint16_t opt_sup_pgsize); void pcie_sriov_config_write(PCIDevice *dev, >> uint32_t address, >> uint32_t val, int len); >> >> -/* Reset SR/IOV VF Enable bit to unregister all VFs */ -void >> pcie_sriov_pf_disable_vfs(PCIDevice *dev); >> +/* Reset SR/IOV */ >> +void pcie_sriov_pf_reset(PCIDevice *dev); >> >> /* Get logical VF number of a VF - only valid for VFs */ uint16_t >> pcie_sriov_vf_number(PCIDevice *dev); diff --git a/hw/net/igb.c >> b/hw/net/igb.c index 0b5c31a58bba..9345506f81ec 100644 >> --- a/hw/net/igb.c >> +++ b/hw/net/igb.c >> @@ -493,7 +493,7 @@ static void igb_qdev_reset_hold(Object *obj) >> >> trace_e1000e_cb_qdev_reset_hold(); >> >> - pcie_sriov_pf_disable_vfs(d); >> + pcie_sriov_pf_reset(d); >> igb_core_reset(&s->core); >> } >> >> diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index >> 7a56e7b79b4d..7c0d3f108724 100644 >> --- a/hw/nvme/ctrl.c >> +++ b/hw/nvme/ctrl.c >> @@ -7116,7 +7116,7 @@ static void nvme_ctrl_reset(NvmeCtrl *n, >> NvmeResetType rst) >> } >> >> if (rst != NVME_RESET_CONTROLLER) { >> - pcie_sriov_pf_disable_vfs(pci_dev); >> + pcie_sriov_pf_reset(pci_dev); >> } >> } >> >> diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index >> da209b7f47fd..51b66d1bb342 100644 >> --- a/hw/pci/pcie_sriov.c >> +++ b/hw/pci/pcie_sriov.c >> @@ -249,16 +249,26 @@ void pcie_sriov_config_write(PCIDevice *dev, >> uint32_t address, } >> >> >> -/* Reset SR/IOV VF Enable bit to trigger an unregister of all VFs */ -void >> pcie_sriov_pf_disable_vfs(PCIDevice *dev) >> +/* Reset SR/IOV */ >> +void pcie_sriov_pf_reset(PCIDevice *dev) >> { >> uint16_t sriov_cap = dev->exp.sriov_cap; >> - if (sriov_cap) { >> - uint32_t val = pci_get_byte(dev->config + sriov_cap + PCI_SRIOV_CTRL); >> - if (val & PCI_SRIOV_CTRL_VFE) { >> - val &= ~PCI_SRIOV_CTRL_VFE; >> - pcie_sriov_config_write(dev, sriov_cap + PCI_SRIOV_CTRL, val, 1); >> - } >> + if (!sriov_cap) { >> + return; >> + } >> + >> + pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); >> + unregister_vfs(dev); >> + >> + /* >> + * Default is to use 4K pages, software can modify it >> + * to any of the supported bits >> + */ >> + pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); >> + > > Just curious, do we need this? > On Linux, I thought the PCI subsystem restores the page size after reset. Perhaps Linux doesn't need it, but the specification requires to reset the whole capability. > > Otherwise, > Assuming change of my mail address from sriram.yagnaraman@est.tech to @ericsson.com is accepted, > Reviewed-by: Sriram Yagnaraman > >> + for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { >> + pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, >> + dev->exp.sriov_pf.vf_bar_type[i]); >> } >> } >> >> >> -- >> 2.43.2