From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [PATCH 9/9] accel/tcg: Remove tlb_flush_page_bits_by_mmuidx_async_1() ???
Date: Tue, 25 May 2021 07:00:00 -0700 [thread overview]
Message-ID: <e6b61b9e-335c-025b-4a86-a616a9833dd3@linaro.org> (raw)
In-Reply-To: <20210509151618.2331764-10-f4bug@amsat.org>
On 5/9/21 8:16 AM, Philippe Mathieu-Daudé wrote:
> From: Richard Henderson<richard.henderson@linaro.org>
>
> Now than ... /* we use range? FILL ME... */ ... we can remove the
> encode_pbm_to_runon() and flush_all_helper() calls.
>
> Signed-off-by: Richard Henderson<richard.henderson@linaro.org>
> Message-Id:<20210508201640.1045808-1-richard.henderson@linaro.org>
> [PMD: Split from bigger patch]
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> XXX proper description, commit might be placed earlier in series.
> ---
> accel/tcg/cputlb.c | 86 +++++++++++-----------------------------------
> 1 file changed, 20 insertions(+), 66 deletions(-)
I think this needs to be sorted before patch 4 (which introduces
tlb_flush_range_by_mmuidx). With commit message:
accel/tcg: Remove {encode,decode}_pbm_to_runon
We will not be able to fit address + length into a 64-bit packet.
Drop this optimization before re-organizing this code.
r~
next prev parent reply other threads:[~2021-05-25 14:02 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-09 15:16 [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages Philippe Mathieu-Daudé
2021-05-09 15:16 ` [PATCH 1/9] accel/tcg: Replace g_new() + memcpy() by g_memdup() Philippe Mathieu-Daudé
2021-05-25 13:31 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 2/9] accel/tcg: Pass length argument to tlb_flush_range_locked() Philippe Mathieu-Daudé
2021-05-09 15:16 ` [PATCH 3/9] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData Philippe Mathieu-Daudé
2021-05-25 13:38 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 4/9] accel/tcg: Add tlb_flush_range_by_mmuidx() Philippe Mathieu-Daudé
2021-05-25 13:42 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 5/9] accel/tcg: Add tlb_flush_page_bits_by_mmuidx_all_cpus() Philippe Mathieu-Daudé
2021-05-25 13:45 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 6/9] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced() Philippe Mathieu-Daudé
2021-05-25 13:46 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 7/9] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0 Philippe Mathieu-Daudé
2021-05-25 13:49 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 8/9] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1] Philippe Mathieu-Daudé
2021-05-25 13:50 ` Richard Henderson
2021-05-09 15:16 ` [PATCH 9/9] accel/tcg: Remove tlb_flush_page_bits_by_mmuidx_async_1() ??? Philippe Mathieu-Daudé
2021-05-25 14:00 ` Richard Henderson [this message]
2021-05-09 15:18 ` [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages Philippe Mathieu-Daudé
2021-05-25 7:55 ` [PATCH v2 " Philippe Mathieu-Daudé
2021-05-25 9:55 ` Peter Maydell
2021-05-25 10:18 ` Philippe Mathieu-Daudé
2021-05-25 14:32 ` [PATCH " Peter Maydell
2021-05-27 16:02 ` Philippe Mathieu-Daudé
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