From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com
Subject: Re: [PATCH v3 3/3] target/riscv: Relax fld alignment requirement
Date: Fri, 2 Aug 2024 17:54:46 +1000 [thread overview]
Message-ID: <e6be2cbe-daf5-40fb-9870-928c86599317@linaro.org> (raw)
In-Reply-To: <20240802072417.659-4-zhiwei_liu@linux.alibaba.com>
On 8/2/24 17:24, LIU Zhiwei wrote:
> According to the risc-v specification:
> "FLD and FSD are only guaranteed to execute atomically if the effective
> address is naturally aligned and XLEN≥64."
>
> We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does
> not violate the rules. But it will hide some problems. So relax it to
> MO_ATOM_NONE.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@linux.alibaba.com>
> ---
> target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2024-08-02 7:55 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-02 7:24 [PATCH v3 0/3] target/riscv: Remove redundant insn length check for zama16b LIU Zhiwei
2024-08-02 7:24 ` [PATCH v3 1/3] " LIU Zhiwei
2024-08-02 7:53 ` Richard Henderson
2024-08-04 23:52 ` Alistair Francis
2024-08-02 7:24 ` [PATCH v3 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b LIU Zhiwei
2024-08-02 7:54 ` Richard Henderson
2024-08-04 23:54 ` Alistair Francis
2024-08-02 7:24 ` [PATCH v3 3/3] target/riscv: Relax fld alignment requirement LIU Zhiwei
2024-08-02 7:54 ` Richard Henderson [this message]
2024-08-04 23:56 ` Alistair Francis
2024-08-05 1:51 ` [PATCH v3 0/3] target/riscv: Remove redundant insn length check for zama16b Alistair Francis
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