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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id p1-20020a1c5441000000b003b4cba4ef71sm19630682wmi.41.2022.11.28.10.20.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Nov 2022 10:20:01 -0800 (PST) Message-ID: Date: Mon, 28 Nov 2022 19:20:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH for-8.0 1/9] hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20221109161444.3397405-1-peter.maydell@linaro.org> <20221109161444.3397405-2-peter.maydell@linaro.org> From: Eric Auger In-Reply-To: <20221109161444.3397405-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eauger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.257, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Peter, On 11/9/22 17:14, Peter Maydell wrote: > Convert the TYPE_ARM_SMMU device to 3-phase reset. The legacy method > doesn't do anything that's invalid in the hold phase, so the > conversion is simple and not a behaviour change. > > Note that we must convert this base class before we can convert the > TYPE_ARM_SMMUV3 subclass -- transitional support in Resettable > handles "chain to parent class reset" when the base class is 3-phase > and the subclass is still using legacy reset, but not the other way > around. > > Signed-off-by: Peter Maydell Reviewed-by: Eric Auger Thanks Eric > --- > hw/arm/smmu-common.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c > index e09b9c13b74..220838525d4 100644 > --- a/hw/arm/smmu-common.c > +++ b/hw/arm/smmu-common.c > @@ -526,9 +526,9 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) > } > } > > -static void smmu_base_reset(DeviceState *dev) > +static void smmu_base_reset_hold(Object *obj) > { > - SMMUState *s = ARM_SMMU(dev); > + SMMUState *s = ARM_SMMU(obj); > > g_hash_table_remove_all(s->configs); > g_hash_table_remove_all(s->iotlb); > @@ -543,12 +543,13 @@ static Property smmu_dev_properties[] = { > static void smmu_base_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass); > > device_class_set_props(dc, smmu_dev_properties); > device_class_set_parent_realize(dc, smmu_base_realize, > &sbc->parent_realize); > - dc->reset = smmu_base_reset; > + rc->phases.hold = smmu_base_reset_hold; > } > > static const TypeInfo smmu_base_info = {