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[176.171.211.120]) by smtp.gmail.com with ESMTPSA id u17-20020adfed51000000b003197efd1e7bsm2114000wro.114.2023.10.05.09.24.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Oct 2023 09:24:23 -0700 (PDT) Message-ID: Date: Thu, 5 Oct 2023 18:24:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v6 14/19] linux-user/riscv: Add vdso Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, laurent@vivier.eu, Alistair Francis References: <20230930021529.987950-1-richard.henderson@linaro.org> <20230930021529.987950-15-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230930021529.987950-15-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-4.219, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 30/9/23 04:15, Richard Henderson wrote: > Acked-by: Alistair Francis > Signed-off-by: Richard Henderson > --- > linux-user/riscv/vdso-asmoffset.h | 9 ++ > linux-user/elfload.c | 2 + > linux-user/riscv/signal.c | 8 ++ > linux-user/meson.build | 1 + > linux-user/riscv/Makefile.vdso | 15 +++ > linux-user/riscv/meson.build | 7 ++ > linux-user/riscv/vdso-32.so | Bin 0 -> 2888 bytes > linux-user/riscv/vdso-64.so | Bin 0 -> 3840 bytes > linux-user/riscv/vdso.S | 186 ++++++++++++++++++++++++++++++ > linux-user/riscv/vdso.ld | 74 ++++++++++++ > 10 files changed, 302 insertions(+) > create mode 100644 linux-user/riscv/vdso-asmoffset.h > create mode 100644 linux-user/riscv/Makefile.vdso > create mode 100644 linux-user/riscv/meson.build > create mode 100755 linux-user/riscv/vdso-32.so > create mode 100755 linux-user/riscv/vdso-64.so > create mode 100644 linux-user/riscv/vdso.S > create mode 100644 linux-user/riscv/vdso.ld Reviewed-by: Philippe Mathieu-Daudé > diff --git a/linux-user/meson.build b/linux-user/meson.build > index dd24389052..3ff3bc5bbc 100644 > --- a/linux-user/meson.build > +++ b/linux-user/meson.build > @@ -45,6 +45,7 @@ subdir('microblaze') > subdir('mips64') > subdir('mips') > subdir('ppc') > +subdir('riscv') > subdir('s390x') > subdir('sh4') > subdir('sparc') We should cover these directories in MAINTAINERS, likely in the "$arch TCG CPUs" sections.