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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH 6/6] accel/tcg: Remain TLB_INVALID_MASK in the address when TLB is re-filled Content-Language: en-US From: Richard Henderson To: Daniel Henrique Barboza , Weiwei Li , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com References: <20230413090122.65228-1-liweiwei@iscas.ac.cn> <20230413090122.65228-7-liweiwei@iscas.ac.cn> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.284, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/18/23 09:18, Richard Henderson wrote: >>> -            /* >>> -             * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, >>> -             * to force the next access through tlb_fill.  We've just >>> -             * called tlb_fill, so we know that this entry *is* valid. >>> -             */ >>> -            flags &= ~TLB_INVALID_MASK; > > > I missed the original patch, but this is definitely wrong. > > Clearing this bit locally (!) is correct because we want to inform the caller of > probe_access_* that the access is valid.  We know that it is valid because we have just > queried tlb_fill (and thus for riscv, PMP). > > Clearing the bit locally does *not* cause the tlb entry to be cached -- the INVALID bit is > still set within the tlb entry.  The next access will again go through tlb_fill. > > What is the original problem you are seeing?  The commit message does not say. From https://lore.kernel.org/qemu-devel/3ace9e9e-91cf-36e6-a18f-494fd44dffab@iscas.ac.cn/ I see that it is a problem with execution. By eye, it appears that get_page_addr_code_hostp needs adjustment, e.g. (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH, cpu_mmu_index(env, true), false, &p, &full, 0); if (p == NULL) { return -1; } + if (full->lg_page_size < TARGET_PAGE_BITS) { + return -1; + } if (hostp) { *hostp = p; } It seems like we could do slightly better than this, perhaps by single-stepping through such a page, but surely this edge case is so uncommon as to not make it worthwhile to consider. r~