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[83.51.160.214]) by smtp.gmail.com with ESMTPSA id u6sm87281815wml.9.2019.08.07.02.50.15 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 02:50:15 -0700 (PDT) To: Bin Meng , Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com> <1565163924-18621-4-git-send-email-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: Date: Wed, 7 Aug 2019 11:50:14 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <1565163924-18621-4-git-send-email-bmeng.cn@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.65 Subject: Re: [Qemu-devel] [PATCH v2 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/7/19 9:44 AM, Bin Meng wrote: > Group SiFive E and U cpu type defines into one header file. > > Signed-off-by: Bin Meng > Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé > --- > > Changes in v2: None > > include/hw/riscv/sifive_cpu.h | 31 +++++++++++++++++++++++++++++++ > include/hw/riscv/sifive_e.h | 7 +------ > include/hw/riscv/sifive_u.h | 7 +------ > 3 files changed, 33 insertions(+), 12 deletions(-) > create mode 100644 include/hw/riscv/sifive_cpu.h > > diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h > new file mode 100644 > index 0000000..1367996 > --- /dev/null > +++ b/include/hw/riscv/sifive_cpu.h > @@ -0,0 +1,31 @@ > +/* > + * SiFive CPU types > + * > + * Copyright (c) 2017 SiFive, Inc. > + * Copyright (c) 2019 Bin Meng > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see . > + */ > + > +#ifndef HW_SIFIVE_CPU_H > +#define HW_SIFIVE_CPU_H > + > +#if defined(TARGET_RISCV32) > +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 > +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 > +#elif defined(TARGET_RISCV64) > +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 > +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 > +#endif > + > +#endif /* HW_SIFIVE_CPU_H */ > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h > index d175b24..e17cdfd 100644 > --- a/include/hw/riscv/sifive_e.h > +++ b/include/hw/riscv/sifive_e.h > @@ -19,6 +19,7 @@ > #ifndef HW_SIFIVE_E_H > #define HW_SIFIVE_E_H > > +#include "hw/riscv/sifive_cpu.h" > #include "hw/riscv/sifive_gpio.h" > > #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" > @@ -83,10 +84,4 @@ enum { > #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 > #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 > > -#if defined(TARGET_RISCV32) > -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 > -#elif defined(TARGET_RISCV64) > -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 > -#endif > - > #endif > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index 892f0ee..4abc621 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -20,6 +20,7 @@ > #define HW_SIFIVE_U_H > > #include "hw/net/cadence_gem.h" > +#include "hw/riscv/sifive_cpu.h" > > #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" > #define RISCV_U_SOC(obj) \ > @@ -77,10 +78,4 @@ enum { > #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 > #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 > > -#if defined(TARGET_RISCV32) > -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 > -#elif defined(TARGET_RISCV64) > -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 > -#endif > - > #endif >