From: Richard Henderson <richard.henderson@linaro.org>
To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
patches@groups.riscv.org
Subject: Re: [Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper
Date: Fri, 25 May 2018 08:20:48 -0700 [thread overview]
Message-ID: <e74f4911-fe58-9884-ea9c-23e13f269700@linaro.org> (raw)
In-Reply-To: <1527034517-7851-7-git-send-email-mjc@sifive.com>
On 05/22/2018 05:14 PM, Michael Clark wrote:
> This patch makes op_helper.c contain only instruction
> operation helpers used by translate.c and moves any
> unrelated cpu helpers into cpu_helper.c. No logic is
> changed by this patch.
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2018-05-25 15:20 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-23 0:14 [Qemu-devel] [PATCH v1 00/30] QEMU 2.13 RISC-V updates Michael Clark
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 01/30] RISC-V: Update address bits to support sv39 and sv48 Michael Clark
2018-05-25 15:07 ` Richard Henderson
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 02/30] RISC-V: Improve page table walker spec compliance Michael Clark
2018-05-23 22:31 ` Michael Clark
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 03/30] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps Michael Clark
2018-05-29 23:32 ` Alistair Francis
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 04/30] RISC-V: Simplify riscv_cpu_local_irqs_pending Michael Clark
2018-05-25 15:15 ` Richard Henderson
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 05/30] RISC-V: Allow setting and clearing multiple irqs Michael Clark
2018-05-23 23:55 ` Alistair Francis
2018-05-25 15:19 ` Richard Henderson
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper Michael Clark
2018-05-23 12:23 ` Philippe Mathieu-Daudé
2018-05-25 15:20 ` Richard Henderson [this message]
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 07/30] RISC-V: Update CSR and interrupt definitions Michael Clark
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 08/30] RISC-V: Implement modular CSR helper interface Michael Clark
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 09/30] RISC-V: Implement atomic mip/sip CSR updates Michael Clark
2018-05-29 23:34 ` Alistair Francis
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 10/30] RISC-V: Implement existential predicates for CSRs Michael Clark
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags Michael Clark
2018-05-23 12:25 ` Philippe Mathieu-Daudé
2018-05-29 23:40 ` Alistair Francis
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 12/30] RISC-V: Mark mstatus.fs dirty Michael Clark
2018-05-29 23:38 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 13/30] RISC-V: Implement mstatus.TSR/TW/TVM Michael Clark
2018-05-23 12:26 ` Philippe Mathieu-Daudé
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging Michael Clark
2018-05-23 12:33 ` Philippe Mathieu-Daudé
2018-05-24 22:47 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers Michael Clark
2018-05-23 12:36 ` Philippe Mathieu-Daudé
2018-05-29 23:43 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Michael Clark
2018-05-23 12:37 ` Philippe Mathieu-Daudé
2018-05-29 23:47 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config Michael Clark
2018-05-23 12:40 ` Philippe Mathieu-Daudé
2018-05-24 22:43 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext Michael Clark
2018-05-23 12:42 ` Philippe Mathieu-Daudé
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 21/30] RISC-V: Add misa.MAFD checks to translate Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support Michael Clark
2018-05-25 18:53 ` Richard Henderson
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes Michael Clark
2018-05-25 22:40 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 24/30] RISC-V: Fix PLIC pending bitfield reads Michael Clark
2018-05-25 22:38 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 25/30] RISC-V: Enable second UART on sifive_e and sifive_u Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 26/30] RISC-V: Remove unnecessary disassembler constraints Michael Clark
2018-05-24 22:45 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines Michael Clark
2018-05-23 6:44 ` Laurent Vivier
2018-05-25 7:17 ` Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 28/30] RISC-V: linux-user support for RVE ABI Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 29/30] RISC-V: Don't add NULL bootargs to device-tree Michael Clark
2018-05-23 12:45 ` Philippe Mathieu-Daudé
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 30/30] RISC-V: Support separate firmware and kernel payload Michael Clark
2018-05-23 12:49 ` Philippe Mathieu-Daudé
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