From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55409) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c2lSI-0000Uu-M3 for qemu-devel@nongnu.org; Fri, 04 Nov 2016 16:51:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c2lSH-0003m3-TD for qemu-devel@nongnu.org; Fri, 04 Nov 2016 16:51:18 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:34114) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c2lSH-0003l3-N1 for qemu-devel@nongnu.org; Fri, 04 Nov 2016 16:51:17 -0400 Received: by mail-wm0-x241.google.com with SMTP id p190so5634259wmp.1 for ; Fri, 04 Nov 2016 13:51:17 -0700 (PDT) From: Artyom Tarasenko Date: Fri, 4 Nov 2016 21:50:06 +0100 Message-Id: In-Reply-To: References: In-Reply-To: References: Subject: [Qemu-devel] [PATCH v1 05/30] target-sparc: add UltraSPARC T1 TLB #defines List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Richard Henderson , Artyom Tarasenko Signed-off-by: Artyom Tarasenko --- target-sparc/cpu.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index b41f5c5..f2e923d 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -336,6 +336,10 @@ enum { #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) +/* UltraSPARC T1 specific */ +#define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ +#define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ + #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ -- 1.8.3.1