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[81.185.167.99]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d0a74d339sm16582165e9.14.2025.03.12.03.27.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 03:27:16 -0700 (PDT) Message-ID: Date: Wed, 12 Mar 2025 11:27:14 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PULL 31/43] hw/arm: Add i.MX 8M Plus EVK board To: Peter Maydell , Thomas Huth , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Cc: qemu-devel@nongnu.org, Bernhard Beschow References: <20250225180510.1318207-1-peter.maydell@linaro.org> <20250225180510.1318207-32-peter.maydell@linaro.org> <1cdb6643-8fcc-4bd8-93fc-fcc93589c9a3@redhat.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org + Cédric for Aspeed On 12/3/25 11:20, Peter Maydell wrote: > On Wed, 12 Mar 2025 at 09:40, Thomas Huth wrote: >> >> On 25/02/2025 19.04, Peter Maydell wrote: >>> From: Bernhard Beschow >>> >>> As a first step, implement the bare minimum: CPUs, RAM, interrupt controller, >>> serial. All other devices of the A53 memory map are represented as >>> TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows >>> for running Linux without it crashing due to invalid memory accesses. >>> >>> Signed-off-by: Bernhard Beschow >>> Message-id: 20250223114708.1780-5-shentey@gmail.com >>> Reviewed-by: Peter Maydell >>> [PMM: drop 'static const' from serial_table[] definition to avoid >>> compile failure on GCC 7.5] >>> Signed-off-by: Peter Maydell >>> --- >> ... >>> +static const TypeInfo fsl_imx8mp_types[] = { >>> + { >>> + .name = TYPE_FSL_IMX8MP, >>> + .parent = TYPE_DEVICE, >>> + .instance_size = sizeof(FslImx8mpState), >>> + .instance_init = fsl_imx8mp_init, >>> + .class_init = fsl_imx8mp_class_init, >>> + }, >>> +}; >>> + >>> +DEFINE_TYPES(fsl_imx8mp_types) >> >> Hi Bernhard, hi Peter, >> >> this device can be used to crash QEMU quite easily: >> >> $ ./qemu-system-aarch64 -M virt -device fsl-imx8mp >> ** >> ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thread: assertion failed: >> (n < tcg_max_ctxs) >> Bail out! ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thread: >> assertion failed: (n < tcg_max_ctxs) >> Aborted (core dumped) >> >> Should it maybe be marked with "user_creatable = false" to avoid this? > > The bug is that this is directly inheriting from TYPE_DEVICE, > not from TYPE_SYSBUS_DEVICE. Doing the former is almost always > wrong, because it means the device is never reset. > > (It looks like we do this wrong for other fsl SoCs too, > but they're marked user_creatable = false.) IIRC it is deliberately that way for the Aspeed SoCs, because otherwise there were issue when building the multi-SoC fby35 machines due to peripherals ending mapped in the same (sys)bus, so developers took a lot of care to not base anything on sysbus. But maybe I'm mis-remembering correctly, the peripherals parent could be sysbus as long as we don't use any sysbus API to map memory regions.