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Tue, 20 Jun 2023 05:09:29 -0700 (PDT) Message-ID: Date: Tue, 20 Jun 2023 14:09:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v1 01/46] target/loongarch: Add LASX data type XReg Content-Language: en-US To: Song Gao , qemu-devel@nongnu.org References: <20230620093814.123650-1-gaosong@loongson.cn> <20230620093814.123650-2-gaosong@loongson.cn> From: Richard Henderson In-Reply-To: <20230620093814.123650-2-gaosong@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/20/23 11:37, Song Gao wrote: > diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h > index b23f38c3d5..347950b4d0 100644 > --- a/target/loongarch/cpu.h > +++ b/target/loongarch/cpu.h > @@ -259,9 +259,23 @@ typedef union VReg { > Int128 Q[LSX_LEN / 128]; > }VReg; > > +#define LASX_LEN (256) > +typedef union XReg { > + int8_t XB[LASX_LEN / 8]; > + int16_t XH[LASX_LEN / 16]; > + int32_t XW[LASX_LEN / 32]; > + int64_t XD[LASX_LEN / 64]; > + uint8_t UXB[LASX_LEN / 8]; > + uint16_t UXH[LASX_LEN / 16]; > + uint32_t UXW[LASX_LEN / 32]; > + uint64_t UXD[LASX_LEN / 64]; > + Int128 XQ[LASX_LEN / 128]; > +} XReg; This is following the example of target/i386, and I think it is a bad example. For Arm, we have one ARMVectorReg which covers AdvSIMD (128-bit) and SVE (2048-bit). I would prefer if you just expand the definition of VReg to be 256 bits. r~