From: Jan Bobek <jan.bobek@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [RISU RFC PATCH v1 2/7] risugen_x86_asm: add module
Date: Fri, 28 Jun 2019 11:57:38 -0400 [thread overview]
Message-ID: <e7b801b7-e999-d96b-19b0-bede9eaf4561@gmail.com> (raw)
In-Reply-To: <55edf7b2-f27e-5dd3-95d9-70e958786699@linaro.org>
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On 6/27/19 5:05 AM, Richard Henderson wrote:
> On 6/19/19 7:04 AM, Jan Bobek wrote:
>> +sub rex_encode(%)
>> +{
>> + my (%args) = @_;
>> +
>> + $args{w} = 0 unless defined $args{w};
>> + $args{r} = 0 unless defined $args{w};
>> + $args{x} = 0 unless defined $args{w};
>> + $args{b} = 0 unless defined $args{w};
>
> What makes you believe that REX.[RXB] are dependent on REX.W?
> Or are these merely cut-and-paste errors?
Oops, that's a typo.
>> +sub modrm_encode(%)
>> +{
>> + my (%args) = @_;
>> +
>> + die "MOD field out-of-range: $args{mod}"
>> + unless 0 <= $args{mod} && $args{mod} <= 3;
>> + die "REG field out-of-range: $args{reg}"
>> + unless 0 <= $args{reg} && $args{reg} <= 7;
>> + die "RM field out-of-range: $args{rm}"
>> + unless 0 <= $args{rm} && $args{rm} <= 7;
>> +
>> + return (value =>
>> + ($args{mod} << 6)
>> + | ($args{reg} << 3)
>> + | $args{rm},
>> + len => 1);
>> +}
>> +
>> +sub sib_encode(%)
>> +{
>> + my (%args) = @_;
>> +
>> + die "SS field out-of-range: $args{ss}"
>> + unless 0 <= $args{ss} && $args{ss} <= 3;
>> + die "INDEX field out-of-range: $args{index}"
>> + unless 0 <= $args{index} && $args{index} <= 7;
>> + die "BASE field out-of-range: $args{base}"
>> + unless 0 <= $args{base} && $args{base} <= 7;
>> +
>> + return (value =>
>> + ($args{ss} << 6)
>> + | ($args{index} << 3)
>> + | $args{base},
>> + len => 1);
>> +}
>
> These are interdependent, in that SIB requires MODRM.RM == 4. But I don't see
> anything that either enforces that or validates it, either here or within
> write_insn below.
It also requires MODRM.MOD != 3. You are right, this is not validated
by the risugen_x86_asm module at all; the caller is supposed to know
what they're doing. I also don't validate if displacement is present
when required; the exact conditions are somewhat complicated, already
present in one form or another in risugen_x86 and it generally seemed
like not worth the effort.
-Jan
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next prev parent reply other threads:[~2019-06-28 16:10 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-19 5:04 [Qemu-devel] [RISU RFC PATCH v1 0/7] Support for generating x86 SSE/SSE2 test images Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 1/7] risugen_common: add insnv, randint_constr, rand_fill Jan Bobek
2019-06-27 8:53 ` Richard Henderson
2019-06-28 15:10 ` Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 2/7] risugen_x86_asm: add module Jan Bobek
2019-06-27 9:05 ` Richard Henderson
2019-06-28 15:57 ` Jan Bobek [this message]
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 3/7] risugen_x86_emit: " Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 4/7] risugen_x86: " Jan Bobek
2019-06-27 10:29 ` Richard Henderson
2019-06-27 10:53 ` Richard Henderson
2019-06-28 16:03 ` Jan Bobek
2019-06-28 17:06 ` Jan Bobek
2019-06-29 12:03 ` Richard Henderson
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 5/7] risugen: allow all byte-aligned instructions Jan Bobek
2019-06-27 10:30 ` Richard Henderson
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 6/7] x86.risu: add SSE instructions Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 7/7] x86.risu: add SSE2 instructions Jan Bobek
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