From: Jiangyifei <jiangyifei@huawei.com>
To: Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: Zhanghailiang <zhang.zhanghailiang@huawei.com>,
"sagark@eecs.berkeley.edu" <sagark@eecs.berkeley.edu>,
"kbastian@mail.uni-paderborn.de" <kbastian@mail.uni-paderborn.de>,
"Zhangxiaofeng \(F\)" <victor.zhangxiaofeng@huawei.com>,
"Alistair.Francis@wdc.com" <Alistair.Francis@wdc.com>,
yinyipeng <yinyipeng1@huawei.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"Wubin \(H\)" <wu.wubin@huawei.com>,
"dengkai \(A\)" <dengkai1@huawei.com>
Subject: RE: [PATCH 3/5] target/riscv: Add H extention state description
Date: Fri, 9 Oct 2020 08:29:03 +0000 [thread overview]
Message-ID: <e7be2fdaaf364c11a1124544da497e4f@huawei.com> (raw)
In-Reply-To: <2e725e26-3952-dbd2-c4aa-d9e933406220@linaro.org>
> -----Original Message-----
> From: Richard Henderson [mailto:richard.henderson@linaro.org]
> Sent: Friday, October 2, 2020 1:28 AM
> To: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org
> Cc: Zhanghailiang <zhang.zhanghailiang@huawei.com>;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Alistair.Francis@wdc.com; yinyipeng
> <yinyipeng1@huawei.com>; palmer@dabbelt.com; Wubin (H)
> <wu.wubin@huawei.com>; dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH 3/5] target/riscv: Add H extention state description
>
> On 9/28/20 9:03 PM, Yifei Jiang wrote:
> > + VMSTATE_UINTTL(env.vsstatus, RISCVCPU),
> > + VMSTATE_UINTTL(env.vstvec, RISCVCPU),
> > + VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
> > + VMSTATE_UINTTL(env.vsepc, RISCVCPU),
> > + VMSTATE_UINTTL(env.vscause, RISCVCPU),
> > + VMSTATE_UINTTL(env.vstval, RISCVCPU),
> > + VMSTATE_UINTTL(env.vsatp, RISCVCPU),
>
> So... if I understand things correctly, this is synthetic state, internal to QEMU.
> It is generally better to only serialize architectural state, so that if qemu
> internals are rearranged, it is easy to decide on the correct sequence of
> operations.
>
> It seems like this should be re-generated with a post_load hook, calling some of
> the code currently in riscv_cpu_swap_hypervisor_regs(). Note that some
> minor rearrangement would be needed to call that code from this new context.
>
>
> r~
Thank you for your comments.
As Alistair said, Those vs* are Virtual Supervisor CSRs. Hypervisor may write those.
Actually，except *_hs, all states are real CSRs and cannot be regenerated.
*_hs are backup of Supervisor CSRs when V=1，so, I don't think could re-generate them.
In conclusion, I think all H extension states in this patch need to be described in vmstate.
Yifei
next prev parent reply other threads:[~2020-10-09 8:30 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-29 2:03 [PATCH 0/5] Support RISC-V migration Yifei Jiang
2020-09-29 2:03 ` [PATCH 1/5] target/riscv: Add basic vmstate description of CPU Yifei Jiang
2020-10-01 17:23 ` Richard Henderson
2020-10-09 8:11 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 2/5] target/riscv: Add PMP state description Yifei Jiang
2020-10-05 22:10 ` Alistair Francis
2020-10-09 8:33 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 3/5] target/riscv: Add H extention " Yifei Jiang
2020-10-01 17:28 ` Richard Henderson
2020-10-05 22:09 ` Alistair Francis
2020-10-09 8:29 ` Jiangyifei [this message]
2020-09-29 2:03 ` [PATCH 4/5] target/riscv: Add V " Yifei Jiang
2020-10-01 17:30 ` Richard Henderson
2020-09-29 2:03 ` [PATCH 5/5] target/riscv: Add sifive_plic vmstate Yifei Jiang
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