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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id du6-20020a056a002b4600b006e5933a0da9sm1733399pfb.165.2024.02.29.15.09.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Feb 2024 15:09:20 -0800 (PST) Message-ID: Date: Thu, 29 Feb 2024 13:09:16 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v5 12/22] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() Content-Language: en-US To: Jinjie Ruan , peter.maydell@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20240229131039.1868904-1-ruanjinjie@huawei.com> <20240229131039.1868904-13-ruanjinjie@huawei.com> From: Richard Henderson In-Reply-To: <20240229131039.1868904-13-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/29/24 03:10, Jinjie Ruan via wrote: > According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt > with superpriority is always IRQ, never FIQ, so the NMI exception trap entry > behave like IRQ. However, VNMI can be IRQ or FIQ, FIQ can only come from > hcrx_el2.HCRX_VFNMI bit, IRQ can be raised from the GIC or come from the > hcrx_el2.HCRX_VINMI bit. > > Signed-off-by: Jinjie Ruan > --- > v4: > - Also handle VNMI in arm_cpu_do_interrupt_aarch64(). > v3: > - Remove the FIQ NMI handle. > --- > target/arm/helper.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index b796dbdf21..bd34b3506a 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -11459,12 +11459,21 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) > break; > case EXCP_IRQ: > case EXCP_VIRQ: > + case EXCP_NMI: > addr += 0x80; > break; > case EXCP_FIQ: > case EXCP_VFIQ: > addr += 0x100; > break; > + case EXCP_VNMI: > + if (env->irq_line_state & CPU_INTERRUPT_VNMI || > + env->cp15.hcrx_el2 & HCRX_VINMI) { > + addr += 0x80; > + } else if (env->cp15.hcrx_el2 & HCRX_VFNMI) { > + addr += 0x100; > + } > + break; By not combining VFNMI with CPU_INTERRUPT_VNMI, you don't need this complication. Just case EXCP_IRQ: case EXCP_VIRQ: + case EXCP_NMI: r~