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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d85afb2d88sm14744599a91.0.2024.09.04.23.56.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Sep 2024 23:56:35 -0700 (PDT) Message-ID: Date: Wed, 4 Sep 2024 23:56:33 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 06/14] tcg/riscv: Implement vector mov/dup{m/i} To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240904142739.854-1-zhiwei_liu@linux.alibaba.com> <20240904142739.854-7-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240904142739.854-7-zhiwei_liu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/4/24 07:27, LIU Zhiwei wrote: > @@ -698,6 +704,21 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) > case TCG_TYPE_I64: > tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); > break; > + case TCG_TYPE_V64: > + case TCG_TYPE_V128: > + case TCG_TYPE_V256: > + { > + int nf = get_vec_type_bytes(type) / riscv_vlenb; > + > + if (nf != 0) { > + tcg_debug_assert(is_power_of_2(nf) && nf <= 8); > + tcg_out_opc_vi(s, OPC_VMVNR_V, ret, arg, nf - 1, true); > + } else { > + riscv_set_vec_config_vl(s, type); > + tcg_out_opc_vv(s, OPC_VMV_V_V, ret, TCG_REG_V0, arg, true); > + } > + } > + break; Perhaps int lmul = type - riscv_lg2_vlenb; int nf = 1 << MIN(lmul, 0); tcg_out_opc_vi(s, OPC_VMVNR_V, ret, arg, nf - 1); Is there a reason to prefer vmv.v.v over vmvnr.v? Seems like we can always move one vector reg... > +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, > + TCGReg dst, int64_t arg) > +{ > + if (arg < 16 && arg >= -16) { > + riscv_set_vec_config_vl_vece(s, type, vece); > + tcg_out_opc_vi(s, OPC_VMV_V_I, dst, TCG_REG_V0, arg, true); > + return; > + } > + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, arg); > + tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); > +} I'll note that 0 and -1 do not require SEW change. I don't know how often that will come up, since in my testing with aarch64, we usually needed to swap to TCG_TYPE_V256 anyway. r~