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([2a01:e0a:280:24f0:9db0:474c:ff43:9f5c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cf276d204asm14048634f8f.24.2025.09.01.00.25.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Sep 2025 00:25:10 -0700 (PDT) Message-ID: Date: Mon, 1 Sep 2025 09:25:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/4] hw/ppc: Add a test machine for the IBM PPE42 CPU To: Glenn Miles , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org References: <20250826201920.335308-1-milesg@linux.ibm.com> <20250826201920.335308-4-milesg@linux.ibm.com> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Content-Language: en-US, fr Autocrypt: addr=clg@redhat.com; keydata= xsFNBFu8o3UBEADP+oJVJaWm5vzZa/iLgpBAuzxSmNYhURZH+guITvSySk30YWfLYGBWQgeo 8NzNXBY3cH7JX3/a0jzmhDc0U61qFxVgrPqs1PQOjp7yRSFuDAnjtRqNvWkvlnRWLFq4+U5t yzYe4SFMjFb6Oc0xkQmaK2flmiJNnnxPttYwKBPd98WfXMmjwAv7QfwW+OL3VlTPADgzkcqj 53bfZ4VblAQrq6Ctbtu7JuUGAxSIL3XqeQlAwwLTfFGrmpY7MroE7n9Rl+hy/kuIrb/TO8n0 ZxYXvvhT7OmRKvbYuc5Jze6o7op/bJHlufY+AquYQ4dPxjPPVUT/DLiUYJ3oVBWFYNbzfOrV RxEwNuRbycttMiZWxgflsQoHF06q/2l4ttS3zsV4TDZudMq0TbCH/uJFPFsbHUN91qwwaN/+ gy1j7o6aWMz+Ib3O9dK2M/j/O/Ube95mdCqN4N/uSnDlca3YDEWrV9jO1mUS/ndOkjxa34ia 70FjwiSQAsyIwqbRO3CGmiOJqDa9qNvd2TJgAaS2WCw/TlBALjVQ7AyoPEoBPj31K74Wc4GS Rm+FSch32ei61yFu6ACdZ12i5Edt+To+hkElzjt6db/UgRUeKfzlMB7PodK7o8NBD8outJGS tsL2GRX24QvvBuusJdMiLGpNz3uqyqwzC5w0Fd34E6G94806fwARAQABzSJDw6lkcmljIExl IEdvYXRlciA8Y2xnQHJlZGhhdC5jb20+wsGRBBMBCAA7FiEEoPZlSPBIlev+awtgUaNDx8/7 7KEFAmTLlVECGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4AACgkQUaNDx8/77KG0eg// S0zIzTcxkrwJ/9XgdcvVTnXLVF9V4/tZPfB7sCp8rpDCEseU6O0TkOVFoGWM39sEMiQBSvyY lHrP7p7E/JYQNNLh441MfaX8RJ5Ul3btluLapm8oHp/vbHKV2IhLcpNCfAqaQKdfk8yazYhh EdxTBlzxPcu+78uE5fF4wusmtutK0JG0sAgq0mHFZX7qKG6LIbdLdaQalZ8CCFMKUhLptW71 xe+aNrn7hScBoOj2kTDRgf9CE7svmjGToJzUxgeh9mIkxAxTu7XU+8lmL28j2L5uNuDOq9vl hM30OT+pfHmyPLtLK8+GXfFDxjea5hZLF+2yolE/ATQFt9AmOmXC+YayrcO2ZvdnKExZS1o8 VUKpZgRnkwMUUReaF/mTauRQGLuS4lDcI4DrARPyLGNbvYlpmJWnGRWCDguQ/LBPpbG7djoy k3NlvoeA757c4DgCzggViqLm0Bae320qEc6z9o0X0ePqSU2f7vcuWN49Uhox5kM5L86DzjEQ RHXndoJkeL8LmHx8DM+kx4aZt0zVfCHwmKTkSTQoAQakLpLte7tWXIio9ZKhUGPv/eHxXEoS 0rOOAZ6np1U/xNR82QbF9qr9TrTVI3GtVe7Vxmff+qoSAxJiZQCo5kt0YlWwti2fFI4xvkOi V7lyhOA3+/3oRKpZYQ86Frlo61HU3r6d9wzOwU0EW7yjdQEQALyDNNMw/08/fsyWEWjfqVhW pOOrX2h+z4q0lOHkjxi/FRIRLfXeZjFfNQNLSoL8j1y2rQOs1j1g+NV3K5hrZYYcMs0xhmrZ KXAHjjDx7FW3sG3jcGjFW5Xk4olTrZwFsZVUcP8XZlArLmkAX3UyrrXEWPSBJCXxDIW1hzwp bV/nVbo/K9XBptT/wPd+RPiOTIIRptjypGY+S23HYBDND3mtfTz/uY0Jytaio9GETj+fFis6 TxFjjbZNUxKpwftu/4RimZ7qL+uM1rG1lLWc9SPtFxRQ8uLvLOUFB1AqHixBcx7LIXSKZEFU CSLB2AE4wXQkJbApye48qnZ09zc929df5gU6hjgqV9Gk1rIfHxvTsYltA1jWalySEScmr0iS YBZjw8Nbd7SxeomAxzBv2l1Fk8fPzR7M616dtb3Z3HLjyvwAwxtfGD7VnvINPbzyibbe9c6g LxYCr23c2Ry0UfFXh6UKD83d5ybqnXrEJ5n/t1+TLGCYGzF2erVYGkQrReJe8Mld3iGVldB7 JhuAU1+d88NS3aBpNF6TbGXqlXGF6Yua6n1cOY2Yb4lO/mDKgjXd3aviqlwVlodC8AwI0Sdu jWryzL5/AGEU2sIDQCHuv1QgzmKwhE58d475KdVX/3Vt5I9kTXpvEpfW18TjlFkdHGESM/Jx IqVsqvhAJkalABEBAAHCwV8EGAECAAkFAlu8o3UCGwwACgkQUaNDx8/77KEhwg//WqVopd5k 8hQb9VVdk6RQOCTfo6wHhEqgjbXQGlaxKHoXywEQBi8eULbeMQf5l4+tHJWBxswQ93IHBQjK yKyNr4FXseUI5O20XVNYDJZUrhA4yn0e/Af0IX25d94HXQ5sMTWr1qlSK6Zu79lbH3R57w9j hQm9emQEp785ui3A5U2Lqp6nWYWXz0eUZ0Tad2zC71Gg9VazU9MXyWn749s0nXbVLcLS0yop s302Gf3ZmtgfXTX/W+M25hiVRRKCH88yr6it+OMJBUndQVAA/fE9hYom6t/zqA248j0QAV/p LHH3hSirE1mv+7jpQnhMvatrwUpeXrOiEw1nHzWCqOJUZ4SY+HmGFW0YirWV2mYKoaGO2YBU wYF7O9TI3GEEgRMBIRT98fHa0NPwtlTktVISl73LpgVscdW8yg9Gc82oe8FzU1uHjU8b10lU XOMHpqDDEV9//r4ZhkKZ9C4O+YZcTFu+mvAY3GlqivBNkmYsHYSlFsbxc37E1HpTEaSWsGfA HQoPn9qrDJgsgcbBVc1gkUT6hnxShKPp4PlsZVMNjvPAnr5TEBgHkk54HQRhhwcYv1T2QumQ izDiU6iOrUzBThaMhZO3i927SG2DwWDVzZltKrCMD1aMPvb3NU8FOYRhNmIFR3fcalYr+9gD uVKe8BVz4atMOoktmt0GWTOC8P4= In-Reply-To: <20250826201920.335308-4-milesg@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/26/25 22:17, Glenn Miles wrote: > Adds a test machine for the IBM PPE42 processor, including a > DEC, FIT, WDT and 1MB of ram. > > The purpose of this machine is only to provide a generic platform > for testing instructions of the recently added PPE42 processor > model which is used extensively in the IBM Power9, Power10 and > future Power server processors. > > Signed-off-by: Glenn Miles > --- > > Changes from previous version > - Added ppe42_machine.c to MAINTAINERS file with self as maintainer > > MAINTAINERS | 6 ++++ > hw/ppc/Kconfig | 9 ++++++ > hw/ppc/meson.build | 2 ++ > hw/ppc/ppc_booke.c | 7 ++++- > hw/ppc/ppe42_machine.c | 69 ++++++++++++++++++++++++++++++++++++++++++ > include/hw/ppc/ppc.h | 1 + > 6 files changed, 93 insertions(+), 1 deletion(-) > create mode 100644 hw/ppc/ppe42_machine.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index a07086ed76..52fa303e0a 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1531,6 +1531,12 @@ F: include/hw/pci-host/grackle.h > F: pc-bios/qemu_vga.ndrv > F: tests/functional/test_ppc_mac.py > > +PPE42 > +M: Glenn Miles > +L: qemu-ppc@nongnu.org > +S: Odd Fixes > +F: hw/ppc/ppe42_machine.c > + > PReP > M: Hervé Poussineau > L: qemu-ppc@nongnu.org > diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig > index ced6bbc740..3fdea5919c 100644 > --- a/hw/ppc/Kconfig > +++ b/hw/ppc/Kconfig > @@ -44,6 +44,15 @@ config POWERNV > select SSI_M25P80 > select PNV_SPI > > +config PPC405 > + bool > + default y > + depends on PPC > + select M48T59 > + select PFLASH_CFI02 > + select PPC4XX > + select SERIAL > + > config PPC440 > bool > default y > diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build > index 9893f8adeb..170b90ae7d 100644 > --- a/hw/ppc/meson.build > +++ b/hw/ppc/meson.build > @@ -57,6 +57,8 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( > 'pnv_n1_chiplet.c', > )) > # PowerPC 4xx boards > +ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( > + 'ppe42_machine.c')) > ppc_ss.add(when: 'CONFIG_PPC440', if_true: files( > 'ppc440_bamboo.c', > 'ppc440_uc.c')) > diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c > index 3872ae2822..13403a56b1 100644 > --- a/hw/ppc/ppc_booke.c > +++ b/hw/ppc/ppc_booke.c > @@ -352,7 +352,12 @@ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags) > booke_timer = g_new0(booke_timer_t, 1); > > cpu->env.tb_env = tb_env; > - tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; > + if (flags & PPC_TIMER_PPE) { PPC_TIMER_PPE definition should be introduced in its own patch. > + /* PPE's use a modified version of the booke behavior */ > + tb_env->flags = flags | PPC_DECR_UNDERFLOW_TRIGGERED; > + } else { > + tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; > + } > > tb_env->tb_freq = freq; > tb_env->decr_freq = freq; > diff --git a/hw/ppc/ppe42_machine.c b/hw/ppc/ppe42_machine.c > new file mode 100644 > index 0000000000..0bc295da28 > --- /dev/null > +++ b/hw/ppc/ppe42_machine.c > @@ -0,0 +1,69 @@ > + > +/* > + * Test Machine for the IBM PPE42 processor > + * > + * Copyright (c) 2025, IBM Corporation. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/units.h" > +#include "qemu/error-report.h" > +#include "system/address-spaces.h" > +#include "hw/boards.h" > +#include "hw/ppc/ppc.h" > +#include "system/system.h" > +#include "system/reset.h" > +#include "system/kvm.h" > + > +static void main_cpu_reset(void *opaque) > +{ > + PowerPCCPU *cpu = opaque; > + > + cpu_reset(CPU(cpu)); There are no register settings ? Just asking > +} > + > +static void ppe42_machine_init(MachineState *machine) > +{ > + PowerPCCPU *cpu; > + CPUPPCState *env; > + > + if (kvm_enabled()) { > + error_report("machine %s does not support the KVM accelerator", > + MACHINE_GET_CLASS(machine)->name); > + exit(EXIT_FAILURE); > + } > + > + /* init CPU */ > + cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); I would introduce a specific MachineState for the ppe42 Machine: struct Ppe42MachineState { /* Private */ MachineState parent_obj; /* Public */ PowerPCCPU cpu; }; and use qdev_realize() too. > + env = &cpu->env; > + if (PPC_INPUT(env) != PPC_FLAGS_INPUT_PPE42) { > + error_report("Incompatible CPU, only PPE42 bus supported"); Can't we define valid_cpu_types instead ? > + exit(1); > + } > + > + qemu_register_reset(main_cpu_reset, cpu); > + > + /* This sets the decrementer timebase */ > + ppc_booke_timers_init(cpu, 37500000, PPC_TIMER_PPE); > + > + /* RAM */ > + if (machine->ram_size > 2 * GiB) { 2GB RAM ? really ? > + error_report("RAM size more than 2 GiB is not supported"); > + exit(1); > + } > + memory_region_add_subregion(get_system_memory(), 0xfff80000, machine->ram); > +} > + > + > +static void ppe42_machine_class_init(MachineClass *mc) > +{ > + mc->desc = "PPE42 Test Machine"; > + mc->init = ppe42_machine_init; > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("PPE42XM"); > + mc->default_ram_id = "ram"; > + mc->default_ram_size = 1 * MiB; > +} > + > +DEFINE_MACHINE("ppe42_machine", ppe42_machine_class_init) > diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h > index 8a14d623f8..cb51d704c6 100644 > --- a/include/hw/ppc/ppc.h > +++ b/include/hw/ppc/ppc.h > @@ -52,6 +52,7 @@ struct ppc_tb_t { > #define PPC_DECR_UNDERFLOW_LEVEL (1 << 4) /* Decr interrupt active when > * the most significant bit is 1. > */ > +#define PPC_TIMER_PPE (1 << 5) /* Enable PPE support */ > > uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset); > void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq);