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Tue, 4 Jul 2023 08:05:27 +0000 (GMT) Message-ID: Subject: Re: [PATCH 05/12] target/s390x: Fix LRA overwriting the top 32 bits on DAT error From: Ilya Leoshkevich To: David Hildenbrand , Laurent Vivier , Richard Henderson Cc: Thomas Huth , qemu-devel@nongnu.org, qemu-s390x@nongnu.org, qemu-stable@nongnu.org Date: Tue, 04 Jul 2023 10:05:26 +0200 In-Reply-To: References: <20230703155801.179167-1-iii@linux.ibm.com> <20230703155801.179167-6-iii@linux.ibm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.48.3 (3.48.3-1.fc38) MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: dJoeK0qhaiV-YNAnllk_o2XF00_W-eQX X-Proofpoint-ORIG-GUID: uCZadksqJMuKL-ose_HYFCThsNRiirs7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-04_04,2023-06-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 phishscore=0 impostorscore=0 spamscore=0 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 priorityscore=1501 mlxlogscore=855 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307040065 Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, 2023-07-04 at 09:47 +0200, David Hildenbrand wrote: > On 03.07.23 17:50, Ilya Leoshkevich wrote: > > When a DAT error occurs, LRA is supposed to write the error > > information > > to the bottom 32 bits of R1, and leave the top 32 bits of R1 alone. > >=20 > > Fix by passing the original value of R1 into helper and copying the > > top 32 bits to the return value. > >=20 > > Fixes: d8fe4a9c284f ("target-s390: Convert LRA") > > Cc: qemu-stable@nongnu.org > > Signed-off-by: Ilya Leoshkevich > > --- > > =C2=A0 target/s390x/helper.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 | 2 +- > > =C2=A0 target/s390x/tcg/mem_helper.c | 4 ++-- > > =C2=A0 target/s390x/tcg/translate.c=C2=A0 | 2 +- > > =C2=A0 3 files changed, 4 insertions(+), 4 deletions(-) > >=20 > > diff --git a/target/s390x/helper.h b/target/s390x/helper.h > > index 6bc01df73d7..05102578fc9 100644 > > --- a/target/s390x/helper.h > > +++ b/target/s390x/helper.h > > @@ -355,7 +355,7 @@ DEF_HELPER_FLAGS_4(idte, TCG_CALL_NO_RWG, void, > > env, i64, i64, i32) > > =C2=A0 DEF_HELPER_FLAGS_4(ipte, TCG_CALL_NO_RWG, void, env, i64, i64, > > i32) > > =C2=A0 DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env) > > =C2=A0 DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env) > > -DEF_HELPER_2(lra, i64, env, i64) > > +DEF_HELPER_3(lra, i64, env, i64, i64) > > =C2=A0 DEF_HELPER_1(per_check_exception, void, env) > > =C2=A0 DEF_HELPER_FLAGS_3(per_branch, TCG_CALL_NO_RWG, void, env, i64, > > i64) > > =C2=A0 DEF_HELPER_FLAGS_2(per_ifetch, TCG_CALL_NO_RWG, void, env, i64) > > diff --git a/target/s390x/tcg/mem_helper.c > > b/target/s390x/tcg/mem_helper.c > > index 84ad85212c9..94d93d7ea78 100644 > > --- a/target/s390x/tcg/mem_helper.c > > +++ b/target/s390x/tcg/mem_helper.c > > @@ -2356,7 +2356,7 @@ void HELPER(purge)(CPUS390XState *env) > > =C2=A0 } > > =C2=A0=20 > > =C2=A0 /* load real address */ > > -uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) > > +uint64_t HELPER(lra)(CPUS390XState *env, uint64_t r1, uint64_t > > addr) > > =C2=A0 { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 uint64_t asc =3D env->psw.mask & PSW_MAS= K_ASC; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 uint64_t ret, tec; > > @@ -2370,7 +2370,7 @@ uint64_t HELPER(lra)(CPUS390XState *env, > > uint64_t addr) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 exc =3D mmu_translate(env, addr, MMU_S39= 0_LRA, asc, &ret, > > &flags, &tec); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (exc) { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cc =3D 3; > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ret =3D exc | 0x80000000; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ret =3D (r1 & 0xFFFFFFFF000= 00000) | exc | 0x80000000; >=20 > ull missing for large constant? Will do. Just for my understanding, why is this necessary? The current code base tends towards using ULL, but it's a little bit inconsistent: $ git grep -i 0xfffffffff | wc -l 2338 $ git grep -i 0xfffffffff | grep -i -v ul | wc -l 95 >=20 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } else { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cc =3D 0; > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ret |=3D addr & = ~TARGET_PAGE_MASK; > > diff --git a/target/s390x/tcg/translate.c > > b/target/s390x/tcg/translate.c > > index 0cef6efbef4..a6079ab7b4f 100644 > > --- a/target/s390x/tcg/translate.c > > +++ b/target/s390x/tcg/translate.c > > @@ -2932,7 +2932,7 @@ static DisasJumpType op_lctlg(DisasContext > > *s, DisasOps *o) > > =C2=A0=20 > > =C2=A0 static DisasJumpType op_lra(DisasContext *s, DisasOps *o) > > =C2=A0 { > > -=C2=A0=C2=A0=C2=A0 gen_helper_lra(o->out, cpu_env, o->in2); > > +=C2=A0=C2=A0=C2=A0 gen_helper_lra(o->out, cpu_env, o->out, o->in2); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 set_cc_static(s); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return DISAS_NEXT; > > =C2=A0 } >=20 > Can't we use something like in1_r1 + wout_r1_32 instead ? *maybe* > cleaner :) >=20 The problem is that we want all 64 bits for the non-error case.