From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 05/13] target/arm: Add some comments in Thumb decode
Date: Wed, 3 Oct 2018 12:32:27 +0200 [thread overview]
Message-ID: <e9753178-49e9-884d-7ce9-faec4e43fee2@redhat.com> (raw)
In-Reply-To: <20181002163556.10279-6-peter.maydell@linaro.org>
On 02/10/2018 18:35, Peter Maydell wrote:
> Add some comments to the Thumb decoder indicating what bits
> of the instruction have been decoded at various points in
> the code.
>
> This is not an exhaustive set of comments; we're gradually
> adding comments as we work with particular bits of the code.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Specifically, I figured these out as I was going through looking
> for the insns which write SP. These comments turn out not to
> be relevant to those instructions, but I don't want to throw
> them away.
> ---
> target/arm/translate.c | 20 +++++++++++++++++---
> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 25a8fe672f5..fcb33b8a503 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -10623,6 +10623,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
> tmp2 = load_reg(s, rm);
> if ((insn & 0x70) != 0)
> goto illegal_op;
> + /*
> + * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx:
> + * - MOV, MOVS (register-shifted register), flagsetting
T2, OK
> + */
> op = (insn >> 21) & 3;
> logic_cc = (insn & (1 << 20)) != 0;
> gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
> @@ -11674,7 +11678,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
> rd = insn & 7;
> op = (insn >> 11) & 3;
> if (op == 3) {
> - /* add/subtract */
> + /*
> + * 0b0001_1xxx_xxxx_xxxx
> + * - Add, subtract (three low registers)
> + * - Add, subtract (two low registers and immediate)
T1, OK
> + */
> rn = (insn >> 3) & 7;
> tmp = load_reg(s, rn);
> if (insn & (1 << 10)) {
> @@ -11711,7 +11719,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
> }
> break;
> case 2: case 3:
> - /* arithmetic large immediate */
> + /*
> + * 0b001x_xxxx_xxxx_xxxx
> + * - Add, subtract, compare, move (one low register and immediate)
T2, OK
> + */
> op = (insn >> 11) & 3;
> rd = (insn >> 8) & 0x7;
> if (op == 0) { /* mov */
> @@ -11848,7 +11859,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
> break;
> }
>
> - /* data processing register */
> + /*
> + * 0b0100_00xx_xxxx_xxxx
> + * - Data-processing (two low registers)
T1, OK
> + */
> rd = insn & 7;
> rm = (insn >> 3) & 7;
> op = (insn >> 6) & 0xf;
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
next prev parent reply other threads:[~2018-10-03 10:32 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-02 16:35 [Qemu-devel] [PATCH 00/13] target/arm: Implement v8M stack limit checks Peter Maydell
2018-10-02 16:35 ` [Qemu-devel] [PATCH 01/13] target/arm: Define new TBFLAG for v8M stack checking Peter Maydell
2018-10-03 19:51 ` Richard Henderson
2018-10-04 16:02 ` Philippe Mathieu-Daudé
2018-10-02 16:35 ` [Qemu-devel] [PATCH 02/13] target/arm: Define new EXCP type for v8M stack overflows Peter Maydell
2018-10-03 8:52 ` Philippe Mathieu-Daudé
2018-10-03 19:52 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 03/13] target/arm: Move v7m_using_psp() to internals.h Peter Maydell
2018-10-03 8:52 ` Philippe Mathieu-Daudé
2018-10-03 19:53 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 04/13] target/arm: Add v8M stack checks on ADD/SUB/MOV of SP Peter Maydell
2018-10-03 20:00 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 05/13] target/arm: Add some comments in Thumb decode Peter Maydell
2018-10-03 10:32 ` Philippe Mathieu-Daudé [this message]
2018-10-03 20:02 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 06/13] target/arm: Add v8M stack checks on exception entry Peter Maydell
2018-10-03 8:58 ` Philippe Mathieu-Daudé
2018-10-03 20:12 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 07/13] target/arm: Add v8M stack limit checks on NS function calls Peter Maydell
2018-10-03 9:02 ` Philippe Mathieu-Daudé
2018-10-03 20:14 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 08/13] target/arm: Add v8M stack checks for LDRD/STRD (imm) Peter Maydell
2018-10-03 14:38 ` Philippe Mathieu-Daudé
2018-10-03 20:16 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 09/13] target/arm: Add v8M stack checks for Thumb2 LDM/STM Peter Maydell
2018-10-03 9:08 ` Philippe Mathieu-Daudé
2018-10-03 20:17 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 10/13] target/arm: Add v8M stack checks for T32 load/store single Peter Maydell
2018-10-03 10:44 ` Philippe Mathieu-Daudé
2018-10-03 20:18 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 11/13] target/arm: Add v8M stack checks for Thumb push/pop Peter Maydell
2018-10-03 9:20 ` Philippe Mathieu-Daudé
2018-10-03 20:19 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 12/13] target/arm: Add v8M stack checks for VLDM/VSTM Peter Maydell
2018-10-03 9:55 ` Philippe Mathieu-Daudé
2018-10-03 20:20 ` Richard Henderson
2018-10-03 20:21 ` Richard Henderson
2018-10-02 16:35 ` [Qemu-devel] [PATCH 13/13] target/arm: Add v8M stack checks for MSR to SP_NS Peter Maydell
2018-10-03 10:18 ` Philippe Mathieu-Daudé
2018-10-03 20:22 ` Richard Henderson
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