From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33775) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZh6r-0002tx-R6 for qemu-devel@nongnu.org; Sun, 01 Jul 2018 14:30:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fZh6q-00074E-O8 for qemu-devel@nongnu.org; Sun, 01 Jul 2018 14:30:05 -0400 Received: from mail-qt0-x235.google.com ([2607:f8b0:400d:c0d::235]:39179) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fZh6q-00073R-J3 for qemu-devel@nongnu.org; Sun, 01 Jul 2018 14:30:04 -0400 Received: by mail-qt0-x235.google.com with SMTP id q12-v6so8236127qtp.6 for ; Sun, 01 Jul 2018 11:30:04 -0700 (PDT) References: <20180520025454.GH3652@lianli.shorne-pla.net> From: Davidson Francis Message-ID: Date: Sun, 1 Jul 2018 15:30:00 -0300 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] OpenRISC - SPR_PICMR always 'OR-ing' the values List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stafford Horne Cc: qemu-devel qemu-devel , Openrisc Hello, Thanks for working on this, your tree works fine here and the issue seems to be fixed, I have nothing to complain about. Regards, Davidson Francis. On 01-07-2018 05:18, Stafford Horne wrote: > Hello, > > We have been working on a few patches to fixed QEMU for OpenRISC and I > included the change for picmr writes, richard added some changes to > SPR writes which might help with the masking/umasking work more > reliably. > > If you want to try them out could you check: > https://github.com/stffrdhrn/qemu/tree/or1k-fixes-212-1 > > Thanks for your help. > > -Stafford > > On Sun, May 20, 2018 at 12:32 PM Davidson Francis > wrote: >> >> Thank you for quick reply, >> >> Yes, I've tried, after that, the register works as expected, but even so, if I >> enable the interrupts right after, I still receive interrupts from the same IRQ, >> but maybe there is something wrong with my code. >> >> Regards, >> Davidson Francis. >> >> 2018-05-19 23:54 GMT-03:00 Stafford Horne : >>> On Sat, May 19, 2018 at 08:08:47PM -0300, Davidson Francis wrote: >>>> Hello Stafford, >>>> >>>> I'm currently using or1k as a target CPU in an operating system that >>>> I'm working. >>>> It happens that I'm having some issues regarding the PICMR register: I realize >>>> that in the latest Qemu version (2.12) when I write into PICMR, the Qemu is >>>> actually 'OR-ing' the values (as I could note in target/openrisc/sys_helper.c >>>> file), so I can't mask an already enabled interrupt. >>>> >>>> I don't know if this behaviour is expected and if so, I'm sorry, but this does >>>> not occurs in the or1ksim, so I thought this could be might an issue. >>> >>> Hello, thanks for pointing this out. It looks wrong to me too. Have you tested >>> changing it to just `env->picmr = rb;`? >>> >>> -Stafford