* Re: [Qemu-devel] OpenRISC - SPR_PICMR always 'OR-ing' the values [not found] <CALAE4RoqNTXyGEUbV3LmonNcyA=o8toPhRrDS23w4W_Zg3z3qg@mail.gmail.com> @ 2018-05-20 2:54 ` Stafford Horne 2018-05-20 3:31 ` Davidson Francis 0 siblings, 1 reply; 5+ messages in thread From: Stafford Horne @ 2018-05-20 2:54 UTC (permalink / raw) To: Davidson Francis; +Cc: QEMU Development, Openrisc On Sat, May 19, 2018 at 08:08:47PM -0300, Davidson Francis wrote: > Hello Stafford, > > I'm currently using or1k as a target CPU in an operating system that > I'm working. > It happens that I'm having some issues regarding the PICMR register: I realize > that in the latest Qemu version (2.12) when I write into PICMR, the Qemu is > actually 'OR-ing' the values (as I could note in target/openrisc/sys_helper.c > file), so I can't mask an already enabled interrupt. > > I don't know if this behaviour is expected and if so, I'm sorry, but this does > not occurs in the or1ksim, so I thought this could be might an issue. Hello, thanks for pointing this out. It looks wrong to me too. Have you tested changing it to just `env->picmr = rb;`? -Stafford ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] OpenRISC - SPR_PICMR always 'OR-ing' the values 2018-05-20 2:54 ` [Qemu-devel] OpenRISC - SPR_PICMR always 'OR-ing' the values Stafford Horne @ 2018-05-20 3:31 ` Davidson Francis 2018-07-01 8:18 ` Stafford Horne 0 siblings, 1 reply; 5+ messages in thread From: Davidson Francis @ 2018-05-20 3:31 UTC (permalink / raw) To: Stafford Horne; +Cc: QEMU Development, Openrisc Thank you for quick reply, Yes, I've tried, after that, the register works as expected, but even so, if I enable the interrupts right after, I still receive interrupts from the same IRQ, but maybe there is something wrong with my code. Regards, Davidson Francis. 2018-05-19 23:54 GMT-03:00 Stafford Horne <shorne@gmail.com>: > On Sat, May 19, 2018 at 08:08:47PM -0300, Davidson Francis wrote: >> Hello Stafford, >> >> I'm currently using or1k as a target CPU in an operating system that >> I'm working. >> It happens that I'm having some issues regarding the PICMR register: I realize >> that in the latest Qemu version (2.12) when I write into PICMR, the Qemu is >> actually 'OR-ing' the values (as I could note in target/openrisc/sys_helper.c >> file), so I can't mask an already enabled interrupt. >> >> I don't know if this behaviour is expected and if so, I'm sorry, but this does >> not occurs in the or1ksim, so I thought this could be might an issue. > > Hello, thanks for pointing this out. It looks wrong to me too. Have you tested > changing it to just `env->picmr = rb;`? > > -Stafford ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] OpenRISC - SPR_PICMR always 'OR-ing' the values 2018-05-20 3:31 ` Davidson Francis @ 2018-07-01 8:18 ` Stafford Horne 2018-07-01 18:30 ` Davidson Francis 0 siblings, 1 reply; 5+ messages in thread From: Stafford Horne @ 2018-07-01 8:18 UTC (permalink / raw) To: Davidson Francis; +Cc: qemu-devel qemu-devel, Openrisc Hello, We have been working on a few patches to fixed QEMU for OpenRISC and I included the change for picmr writes, richard added some changes to SPR writes which might help with the masking/umasking work more reliably. If you want to try them out could you check: https://github.com/stffrdhrn/qemu/tree/or1k-fixes-212-1 Thanks for your help. -Stafford On Sun, May 20, 2018 at 12:32 PM Davidson Francis <davidsondfgl@gmail.com> wrote: > > Thank you for quick reply, > > Yes, I've tried, after that, the register works as expected, but even so, if I > enable the interrupts right after, I still receive interrupts from the same IRQ, > but maybe there is something wrong with my code. > > Regards, > Davidson Francis. > > 2018-05-19 23:54 GMT-03:00 Stafford Horne <shorne@gmail.com>: > > On Sat, May 19, 2018 at 08:08:47PM -0300, Davidson Francis wrote: > >> Hello Stafford, > >> > >> I'm currently using or1k as a target CPU in an operating system that > >> I'm working. > >> It happens that I'm having some issues regarding the PICMR register: I realize > >> that in the latest Qemu version (2.12) when I write into PICMR, the Qemu is > >> actually 'OR-ing' the values (as I could note in target/openrisc/sys_helper.c > >> file), so I can't mask an already enabled interrupt. > >> > >> I don't know if this behaviour is expected and if so, I'm sorry, but this does > >> not occurs in the or1ksim, so I thought this could be might an issue. > > > > Hello, thanks for pointing this out. It looks wrong to me too. Have you tested > > changing it to just `env->picmr = rb;`? > > > > -Stafford ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] OpenRISC - SPR_PICMR always 'OR-ing' the values 2018-07-01 8:18 ` Stafford Horne @ 2018-07-01 18:30 ` Davidson Francis 2018-07-01 19:46 ` Stafford Horne 0 siblings, 1 reply; 5+ messages in thread From: Davidson Francis @ 2018-07-01 18:30 UTC (permalink / raw) To: Stafford Horne; +Cc: qemu-devel qemu-devel, Openrisc Hello, Thanks for working on this, your tree works fine here and the issue seems to be fixed, I have nothing to complain about. Regards, Davidson Francis. On 01-07-2018 05:18, Stafford Horne wrote: > Hello, > > We have been working on a few patches to fixed QEMU for OpenRISC and I > included the change for picmr writes, richard added some changes to > SPR writes which might help with the masking/umasking work more > reliably. > > If you want to try them out could you check: > https://github.com/stffrdhrn/qemu/tree/or1k-fixes-212-1 > > Thanks for your help. > > -Stafford > > On Sun, May 20, 2018 at 12:32 PM Davidson Francis > <davidsondfgl@gmail.com> wrote: >> >> Thank you for quick reply, >> >> Yes, I've tried, after that, the register works as expected, but even so, if I >> enable the interrupts right after, I still receive interrupts from the same IRQ, >> but maybe there is something wrong with my code. >> >> Regards, >> Davidson Francis. >> >> 2018-05-19 23:54 GMT-03:00 Stafford Horne <shorne@gmail.com>: >>> On Sat, May 19, 2018 at 08:08:47PM -0300, Davidson Francis wrote: >>>> Hello Stafford, >>>> >>>> I'm currently using or1k as a target CPU in an operating system that >>>> I'm working. >>>> It happens that I'm having some issues regarding the PICMR register: I realize >>>> that in the latest Qemu version (2.12) when I write into PICMR, the Qemu is >>>> actually 'OR-ing' the values (as I could note in target/openrisc/sys_helper.c >>>> file), so I can't mask an already enabled interrupt. >>>> >>>> I don't know if this behaviour is expected and if so, I'm sorry, but this does >>>> not occurs in the or1ksim, so I thought this could be might an issue. >>> >>> Hello, thanks for pointing this out. It looks wrong to me too. Have you tested >>> changing it to just `env->picmr = rb;`? >>> >>> -Stafford ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] OpenRISC - SPR_PICMR always 'OR-ing' the values 2018-07-01 18:30 ` Davidson Francis @ 2018-07-01 19:46 ` Stafford Horne 0 siblings, 0 replies; 5+ messages in thread From: Stafford Horne @ 2018-07-01 19:46 UTC (permalink / raw) To: Davidson Francis; +Cc: qemu-devel qemu-devel, Openrisc, Richard Henderson +cc Richard On Mon, Jul 2, 2018, 3:30 AM Davidson Francis <davidsondfgl@gmail.com> wrote: > Hello, > > Thanks for working on this, your tree works fine here and the issue > seems to be fixed, I have nothing to complain about. > Great news. -Stafford Regards, > Davidson Francis. > > On 01-07-2018 05:18, Stafford Horne wrote: > > Hello, > > > > We have been working on a few patches to fixed QEMU for OpenRISC and I > > included the change for picmr writes, richard added some changes to > > SPR writes which might help with the masking/umasking work more > > reliably. > > > > If you want to try them out could you check: > > https://github.com/stffrdhrn/qemu/tree/or1k-fixes-212-1 > > > > Thanks for your help. > > > > -Stafford > > > > On Sun, May 20, 2018 at 12:32 PM Davidson Francis > > <davidsondfgl@gmail.com> wrote: > >> > >> Thank you for quick reply, > >> > >> Yes, I've tried, after that, the register works as expected, but even > so, if I > >> enable the interrupts right after, I still receive interrupts from the > same IRQ, > >> but maybe there is something wrong with my code. > >> > >> Regards, > >> Davidson Francis. > >> > >> 2018-05-19 23:54 GMT-03:00 Stafford Horne <shorne@gmail.com>: > >>> On Sat, May 19, 2018 at 08:08:47PM -0300, Davidson Francis wrote: > >>>> Hello Stafford, > >>>> > >>>> I'm currently using or1k as a target CPU in an operating system that > >>>> I'm working. > >>>> It happens that I'm having some issues regarding the PICMR register: > I realize > >>>> that in the latest Qemu version (2.12) when I write into PICMR, the > Qemu is > >>>> actually 'OR-ing' the values (as I could note in > target/openrisc/sys_helper.c > >>>> file), so I can't mask an already enabled interrupt. > >>>> > >>>> I don't know if this behaviour is expected and if so, I'm sorry, but > this does > >>>> not occurs in the or1ksim, so I thought this could be might an issue. > >>> > >>> Hello, thanks for pointing this out. It looks wrong to me too. Have > you tested > >>> changing it to just `env->picmr = rb;`? > >>> > >>> -Stafford > ^ permalink raw reply [flat|nested] 5+ messages in thread
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2018-05-20 2:54 ` [Qemu-devel] OpenRISC - SPR_PICMR always 'OR-ing' the values Stafford Horne
2018-05-20 3:31 ` Davidson Francis
2018-07-01 8:18 ` Stafford Horne
2018-07-01 18:30 ` Davidson Francis
2018-07-01 19:46 ` Stafford Horne
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