From: Richard Henderson <richard.henderson@linaro.org>
To: Lawrence Hunter <lawrence.hunter@codethink.co.uk>, qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, pbonzini@redhat.com,
philipp.tomsich@vrull.eu, kvm@vger.kernel.org,
qemu-riscv@nongnu.org
Subject: Re: [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops
Date: Mon, 1 May 2023 21:20:02 +0100 [thread overview]
Message-ID: <e9d647a3-c98e-7ab8-9378-74ac2d867a28@linaro.org> (raw)
In-Reply-To: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk>
On 4/28/23 15:47, Lawrence Hunter wrote:
> From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
>
> This commit adds helper functions and tcg operation definitions for the andcs and rotrs instructions
>
> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
> ---
> accel/tcg/tcg-runtime-gvec.c | 11 +++++++++++
> accel/tcg/tcg-runtime.h | 1 +
> include/tcg/tcg-op-gvec.h | 4 ++++
> tcg/tcg-op-gvec.c | 23 +++++++++++++++++++++++
> 4 files changed, 39 insertions(+)
Queued to tcg-next as two patches, and with alterations:
> +void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs,
> + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
> +{
> + static GVecGen2s g = {
> + .fni8 = tcg_gen_andc_i64,
> + .fniv = tcg_gen_andc_vec,
> + .fno = gen_helper_gvec_andcs,
> + .prefer_i64 = TCG_TARGET_REG_BITS == 64,
> + .vece = MO_64
> + };
> +
> + tcg_gen_dup_i64(vece, c, c);
> + tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g);
> +}
This needed a temporary.
> +void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs,
> + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
> +{
> + TCGv_i32 tmp = tcg_temp_new_i32();
> + tcg_gen_sub_i32(tmp, tcg_constant_i32(1 << (vece + 3)), shift);
> + tcg_gen_gvec_rotls(vece, dofs, aofs, tmp, oprsz, maxsz);
> +}
This needed the rotation count to be masked (32 - 0 == 32 is illegal).
Simplified as (-shift & mask).
r~
next prev parent reply other threads:[~2023-05-01 20:20 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 14:47 [PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-04-29 1:29 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro Lawrence Hunter
2023-04-29 1:31 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks Lawrence Hunter
2023-04-29 2:36 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support Lawrence Hunter
2023-04-29 2:58 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 05/19] target/riscv: Move vector translation checks Lawrence Hunter
2023-04-29 3:04 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction Lawrence Hunter
2023-04-29 3:06 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-04-29 3:10 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts Lawrence Hunter
2023-05-01 19:56 ` Richard Henderson
2023-05-02 20:11 ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops Lawrence Hunter
2023-05-01 20:20 ` Richard Henderson [this message]
2023-04-28 14:47 ` [PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers Lawrence Hunter
2023-05-01 19:56 ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support Lawrence Hunter
2023-04-29 3:15 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 12/19] target/riscv: Add Zvkned " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 13/19] target/riscv: Add Zvknh " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 14/19] target/riscv: Add Zvksh " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 15/19] target/riscv: Add Zvkg " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 16/19] crypto: Create sm4_subword Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 17/19] crypto: Add SM4 constant parameter CK Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 18/19] target/riscv: Add Zvksed ISA extension support Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties Lawrence Hunter
2023-04-29 3:21 ` Weiwei Li
2023-06-16 9:21 ` [PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support Daniel Henrique Barboza
2023-06-16 15:03 ` Max Chou
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