Re: [PATCH v5 06/30] tcg/loongarch64: Define the operand constraints

["Philippe Mathieu-Daudé" <f4bug@amsat.org>]

On 9/24/21 19:25, WANG Xuerui wrote:
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/loongarch64/tcg-target-con-str.h | 28 +++++++++++++++
>   tcg/loongarch64/tcg-target.c.inc     | 52 ++++++++++++++++++++++++++++
>   2 files changed, 80 insertions(+)
>   create mode 100644 tcg/loongarch64/tcg-target-con-str.h
> 
> diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-target-con-str.h
> new file mode 100644
> index 0000000000..c3986a4fd4
> --- /dev/null
> +++ b/tcg/loongarch64/tcg-target-con-str.h
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Define LoongArch target-specific operand constraints.
> + *
> + * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
> + *
> + * Based on tcg/riscv/tcg-target-con-str.h
> + *
> + * Copyright (c) 2021 Linaro
> + */
> +
> +/*
> + * Define constraint letters for register sets:
> + * REGS(letter, register_mask)
> + */
> +REGS('r', ALL_GENERAL_REGS)
> +REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
> +
> +/*
> + * Define constraint letters for constants:
> + * CONST(letter, TCG_CT_CONST_* bit set)
> + */
> +CONST('I', TCG_CT_CONST_S12)
> +CONST('N', TCG_CT_CONST_N12)
> +CONST('U', TCG_CT_CONST_U12)
> +CONST('Z', TCG_CT_CONST_ZERO)
> +CONST('C', TCG_CT_CONST_C12)
> +CONST('W', TCG_CT_CONST_WSZ)
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index 42eebef78e..f0930f77ef 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -116,3 +116,55 @@ static const int tcg_target_call_oarg_regs[] = {
>       TCG_REG_A0,
>       TCG_REG_A1,
>   };
> +
> +#define TCG_CT_CONST_ZERO  0x100
> +#define TCG_CT_CONST_S12   0x200
> +#define TCG_CT_CONST_N12   0x400
> +#define TCG_CT_CONST_U12   0x800
> +#define TCG_CT_CONST_C12   0x1000
> +#define TCG_CT_CONST_WSZ   0x2000
> +
> +#define ALL_GENERAL_REGS      MAKE_64BIT_MASK(0, 32)
> +/*
> + * For softmmu, we need to avoid conflicts with the first 5
> + * argument registers to call the helper.  Some of these are
> + * also used for the tlb lookup.
> + */
> +#ifdef CONFIG_SOFTMMU
> +#define SOFTMMU_RESERVE_REGS  MAKE_64BIT_MASK(TCG_REG_A0, 5)
> +#else
> +#define SOFTMMU_RESERVE_REGS  0
> +#endif
> +
> +
> +static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
> +{
> +    return sextract64(val, pos, len);
> +}
> +
> +/* test if a constant matches the constraint */
> +static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
> +{
> +    if (ct & TCG_CT_CONST) {
> +        return 1;
> +    }
> +    if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
> +        return 1;
> +    }
> +    if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
> +        return 1;
> +    }
> +    if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
> +        return 1;
> +    }
> +    if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) {
> +        return 1;
> +    }
> +    if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) {
> +        return 1;
> +    }
> +    if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
> +        return 1;
> +    }
> +    return 0;

Replacing 1 -> true and 0 -> false:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> +}
>