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Tue, 24 Sep 2019 14:33:17 -0700 (PDT) Received: from [172.20.32.216] ([12.157.10.114]) by smtp.gmail.com with ESMTPSA id z13sm6310653pfq.121.2019.09.24.14.33.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Sep 2019 14:33:16 -0700 (PDT) Subject: Re: [PATCH 3/7] target/ppc: update {get, set}_dfp{64, 128}() helper functions to read/write DFP numbers correctly To: Mark Cave-Ayland , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, pc@us.ibm.com, david@gibson.dropbear.id.au References: <20190924153556.27575-1-mark.cave-ayland@ilande.co.uk> <20190924153556.27575-4-mark.cave-ayland@ilande.co.uk> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: Date: Tue, 24 Sep 2019 14:33:14 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190924153556.27575-4-mark.cave-ayland@ilande.co.uk> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.210.195 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/24/19 8:35 AM, Mark Cave-Ayland wrote: > Since commit ef96e3ae96 "target/ppc: move FP and VMX registers into aligned vsr > register array" FP registers are no longer stored consecutively in memory and so > the current method of combining FP register pairs into DFP numbers is incorrect. > > Firstly update the definition of the dh_*_fprp defines in helper.h to reflect > that FP registers are now stored as part of an array of ppc_vsr_t elements > rather than plain uint64_t elements, and then introduce a new ppc_fprp_t type > which conceptually represents a DFP even-odd register pair to be consumed by the > DFP helper functions. > > Finally update the new DFP {get,set}_dfp{64,128}() helper functions to convert > between DFP numbers and DFP even-odd register pairs correctly, making use of the > existing VsrD() macro to access the correct elements regardless of host endian. > > Fixes: ef96e3ae96 "target/ppc: move FP and VMX registers into aligned vsr register array" > Signed-off-by: Mark Cave-Ayland > --- > target/ppc/cpu.h | 1 + > target/ppc/dfp_helper.c | 80 +++++++++++++++++++++-------------------- > target/ppc/helper.h | 2 +- > 3 files changed, 44 insertions(+), 39 deletions(-) Yay! I really was getting ahead of things. Reviewed-by: Richard Henderson r~