Re: [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops

[Richard Henderson <richard.henderson@linaro.org>]

On 9/4/24 08:25, LIU Zhiwei wrote:
>> I'm trying to work out how much benefit there is here of expanding these early, as 
>> opposed to simply using TCG_REG_TMP0 when the immediate doesn't fit,
> 
> We find for rotli,  it just copied code from the implementation of INDEX_op_shli_vec and 
> INDEX_op_shri_vec if we don't expand it.
> 
>    case INDEX_op_rotli_vec:
>          if (a2 > 31) {
>              tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, TCG_REG_ZERO, a2);
>              tcg_out_opc_vx(s, OPC_VSLL_VX, TCG_REG_V0, a1, TCG_REG_TMP0, true);
>          } else {
>              tcg_out_opc_vi(s, OPC_VSLL_VI, TCG_REG_V0, a1, a2, true);
>          }
> 
>          if ((8 << vece) - a2) > 31) {
>              tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, TCG_REG_ZERO, 8 << vece) - a2);
>              tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, TCG_REG_TMP0, true);
>          } else {
>              tcg_out_opc_vi(s, OPC_VSRL_VI, a0, a1, 8 << vece) - a2, true);
>          }
>          tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0, true);
>          break;
> 
> Thus, I prefer to expand it early, at least for rotli_vec.

static void tcg_out_vshifti(TCGContext *s, RISCVInsn op_vi, RISCVInsn op_vx,
                             TCGReg dst, TCGReg src, unsigned imm)
{
     if (imm < 32) {
         tcg_out_opc_vi(s, op_vi, dst, src, imm);
     } else {
         tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP0, imm);
         tcg_out_opc_vx(s, op_vx, dst, src, TCG_REG_TMP0);
     }
}


     case INDEX_op_shli_vec:
         set_vconfig_vl_sew(s, type, vece);
         tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, a0, a1, a2);
         break;

     case INDEX_op_rotli_vec:
         set_vconfig_vl_sew(s, type, vece);
         tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, TCG_REG_V0, a1, a2);
         a2 = -a2 & ((8 << vece) - 1);
         tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1, a2);
         tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0);
         break;

r~