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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-206ae9138b5sm16777795ad.50.2024.09.04.12.05.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Sep 2024 12:05:26 -0700 (PDT) Message-ID: Date: Wed, 4 Sep 2024 12:05:24 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> <20240830061607.1940-14-zhiwei_liu@linux.alibaba.com> <97873524-9e47-44c4-b34a-a27e9833b0e1@linaro.org> <141dbbff-55f6-4628-9701-554b0d32440d@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <141dbbff-55f6-4628-9701-554b0d32440d@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/4/24 08:25, LIU Zhiwei wrote: >> I'm trying to work out how much benefit there is here of expanding these early, as >> opposed to simply using TCG_REG_TMP0 when the immediate doesn't fit, > > We find for rotli,  it just copied code from the implementation of INDEX_op_shli_vec and > INDEX_op_shri_vec if we don't expand it. > > case INDEX_op_rotli_vec: > if (a2 > 31) { > tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, TCG_REG_ZERO, a2); > tcg_out_opc_vx(s, OPC_VSLL_VX, TCG_REG_V0, a1, TCG_REG_TMP0, true); > } else { > tcg_out_opc_vi(s, OPC_VSLL_VI, TCG_REG_V0, a1, a2, true); > } > > if ((8 << vece) - a2) > 31) { > tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, TCG_REG_ZERO, 8 << vece) - a2); > tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, TCG_REG_TMP0, true); > } else { > tcg_out_opc_vi(s, OPC_VSRL_VI, a0, a1, 8 << vece) - a2, true); > } > tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0, true); > break; > > Thus, I prefer to expand it early, at least for rotli_vec. static void tcg_out_vshifti(TCGContext *s, RISCVInsn op_vi, RISCVInsn op_vx, TCGReg dst, TCGReg src, unsigned imm) { if (imm < 32) { tcg_out_opc_vi(s, op_vi, dst, src, imm); } else { tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP0, imm); tcg_out_opc_vx(s, op_vx, dst, src, TCG_REG_TMP0); } } case INDEX_op_shli_vec: set_vconfig_vl_sew(s, type, vece); tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, a0, a1, a2); break; case INDEX_op_rotli_vec: set_vconfig_vl_sew(s, type, vece); tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, TCG_REG_V0, a1, a2); a2 = -a2 & ((8 << vece) - 1); tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1, a2); tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); break; r~