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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id ml8sm6051475pjb.47.2020.07.10.10.51.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Jul 2020 10:51:09 -0700 (PDT) Subject: Re: [RFC 12/65] target/riscv: rvv-0.9: update check functions To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20200710104920.13550-1-frank.chang@sifive.com> <20200710104920.13550-13-frank.chang@sifive.com> From: Richard Henderson Message-ID: Date: Fri, 10 Jul 2020 10:51:06 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200710104920.13550-13-frank.chang@sifive.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , LIU Zhiwei , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/10/20 3:48 AM, frank.chang@sifive.com wrote: > +#define REQUIRE_RVV do { \ > + if (s->mstatus_vs == 0) \ > + return false; \ > +} while (0) You've used this macro already back in patch 7. I guess it should not have been there? Or this bit belongs there, one or the other. I think this patch requires a description and justification. I have no idea why you are replacing > - return (vext_check_isa_ill(s) && > - vext_check_overlap_mask(s, a->rd, a->vm, false) && > - vext_check_reg(s, a->rd, false) && > - vext_check_reg(s, a->rs2, false) && > - vext_check_reg(s, a->rs1, false)); with invisible returns > + REQUIRE_RVV; > + VEXT_CHECK_ISA_ILL(s); > + VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true); > + return true; r~