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[156.19.246.23]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fceb0499d8sm8863158a91.11.2025.02.25.11.25.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Feb 2025 11:25:26 -0800 (PST) Message-ID: Date: Tue, 25 Feb 2025 11:25:24 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 006/162] tcg: Convert and to TCGOutOpBinary To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org References: <20250216231012.2808572-1-richard.henderson@linaro.org> <20250216231012.2808572-7-richard.henderson@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/25/25 10:40, Philippe Mathieu-Daudé wrote: >> diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc >> index 1115d1e38d..01010dfdc0 100644 >> --- a/tcg/i386/tcg-target.c.inc >> +++ b/tcg/i386/tcg-target.c.inc > > >> +static void tgen_andi(TCGContext *s, TCGType type, >> +                      TCGReg a0, TCGReg a1, tcg_target_long a2) >> +{ >> +    int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; >> +    tgen_arithi(s, ARITH_AND + rexw, a0, a2, 0); > > We could s/0/false/ in preparation of tgen_arithi() taking a boolean > for the CF bit. Ok. >> +++ b/tcg/s390x/tcg-target.c.inc >> @@ -2196,6 +2196,31 @@ static const TCGOutOpBinary outop_add = { >>       .out_rri = tgen_addi, >>   }; >> +static void tgen_and(TCGContext *s, TCGType type, >> +                     TCGReg a0, TCGReg a1, TCGReg a2) >> +{ >> +    if (type != TCG_TYPE_I32) { >> +        tcg_out_insn(s, RRFa, NGRK, a0, a1, a2); >> +    } else if (a0 == a1) { >> +        tcg_out_insn(s, RR, NR, a0, a2); >> +    } else { >> +        tcg_out_insn(s, RRFa, NRK, a0, a1, a2); >> +    } >> +} >> + >> +static void tgen_andi_3(TCGContext *s, TCGType type, >> +                        TCGReg a0, TCGReg a1, tcg_target_long a2) >> +{ >> +    tcg_out_mov(s, type, a0, a1); >> +    tgen_andi(s, type, a0, a2); >> +} >> + >> +static const TCGOutOpBinary outop_and = { >> +    .base.static_constraint = C_O1_I2(r, r, rNKR), > > So INDEX_op_and_i32 gets more constraints (ri -> rNKR): > > CONST('K', TCG_CT_CONST_P32) > CONST('N', TCG_CT_CONST_INV) > CONST('R', TCG_CT_CONST_INVRISBG) > > IIUC this doesn't affect anything, as these constraints are only > useful for 64-bit ops, right? Yes, as with the similar question vs addition, TCG_CT_CONST_P32 will match all TCG_TYPE_I32. >> +++ b/tcg/sparc64/tcg-target.c.inc > > >> +static const TCGOutOpBinary outop_and = { >> +    .base.static_constraint = C_O1_I2(r, r, rJ), > > Again, missing 'z', so C_O1_I2(r, rz, rJ)? Again, eliminating impossible constraints. AND shares the same assert for non-constant as ADD. r~