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Tue, 23 Sep 2025 13:08:40 -0700 (PDT) Received: from [192.168.0.4] ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-26980053dc8sm171070535ad.13.2025.09.23.13.08.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Sep 2025 13:08:40 -0700 (PDT) Message-ID: Date: Tue, 23 Sep 2025 13:08:38 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/2] target/arm: Implement ID_AA64PFR2_EL1 To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20250923175751.966795-1-peter.maydell@linaro.org> From: Richard Henderson Content-Language: en-US In-Reply-To: <20250923175751.966795-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/23/25 10:57, Peter Maydell wrote: > The ID register ID_AA64PFR2_EL1 is in the space previously reserved > in the system register ID space, but recent versions of the > architecture have started to define fields in it to advertise the > presence of new architectural features. We don't implement any > of those new features yet, but will need to do so at some point. > (Notably, the GICv5 EAC spec defines a field in this register > to advertise the GICv5 CPU interface.) > > This patchset gives ID_AA64PFR2_EL1 a backing field in the CPU > ID regs struct, defines the field names, and reads it from KVM if > it's present there. The only visible behaviour change is the > name we present to the user via the gdbstub. > > Commit 1 is a code movement one to clear some more stuff out > of cpu.h that doesn't need to be there; it's mostly because of that > that I'm sending this patchset rather than holding on to it until > I have some GICv5 patches ready to send. > > (Compare commit f7ddd7b6a1f90c from last year which added the > ID_AA64MMFR3_EL1 register.) > > v2 here is just a rebase which updates the patchset to handle > the new array-based storage we're using for ID register values. > > thanks > -- PMM > > Peter Maydell (2): > target/arm: Move ID register field defs to cpu-features.h > target/arm: Implement ID_AA64PFR2_EL1 > Reviewed-by: Richard Henderson r~