From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Bin Meng <bmeng@tinylab.org>, qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order
Date: Thu, 8 Dec 2022 11:40:28 +0100 [thread overview]
Message-ID: <ea5ce917-9d27-e22d-2ba8-22439c6b6147@linaro.org> (raw)
In-Reply-To: <20221207100335.290481-4-bmeng@tinylab.org>
On 7/12/22 11:03, Bin Meng wrote:
> SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v1)
>
> hw/riscv/Kconfig | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2022-12-08 10:40 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-07 10:03 ` [PATCH v2 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-08 10:38 ` Philippe Mathieu-Daudé
2022-12-07 10:03 ` [PATCH v2 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
2022-12-07 10:03 ` [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
2022-12-08 10:40 ` Philippe Mathieu-Daudé [this message]
2022-12-08 22:45 ` Wilfred Mallawa
2022-12-07 10:03 ` [PATCH v2 05/16] hw/riscv: spike: Remove misleading comments Bin Meng
2022-12-07 10:03 ` [PATCH v2 06/16] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
2022-12-07 10:03 ` [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
2022-12-07 10:03 ` [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Bin Meng
2022-12-08 4:18 ` Alistair Francis
2022-12-08 10:40 ` Philippe Mathieu-Daudé
2022-12-07 10:03 ` [PATCH v2 09/16] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
2022-12-07 10:03 ` [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
2022-12-07 10:03 ` [PATCH v2 11/16] hw/riscv: sifive_e: " Bin Meng
2022-12-07 10:03 ` [PATCH v2 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
2022-12-07 10:03 ` [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
2022-12-07 10:03 ` [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
2022-12-08 22:49 ` Wilfred Mallawa
2022-12-07 10:03 ` [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
2022-12-07 10:03 ` [PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
2022-12-08 10:38 ` [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Philippe Mathieu-Daudé
2022-12-08 22:46 ` Wilfred Mallawa
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