* [PATCH v2 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-08 10:38 ` Philippe Mathieu-Daudé
2022-12-07 10:03 ` [PATCH v2 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
` (15 subsequent siblings)
16 siblings, 1 reply; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, Anup Patel, Peter Maydell, Richard Henderson,
Song Gao, Xiaojuan Yang
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in both riscv_aplic_realize() and
riscv_imsic_realize().
Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/intc/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 1d4573e803..21441d0a0c 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -72,9 +72,11 @@ config RISCV_ACLINT
config RISCV_APLIC
bool
+ select MSI_NONBROKEN
config RISCV_IMSIC
bool
+ select MSI_NONBROKEN
config SIFIVE_PLIC
bool
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
2022-12-07 10:03 ` [PATCH v2 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
@ 2022-12-08 10:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-12-08 10:38 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Alistair Francis, Anup Patel, Peter Maydell, Richard Henderson,
Song Gao, Xiaojuan Yang
On 7/12/22 11:03, Bin Meng wrote:
> hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
> controllers regardless of how MSI is implemented. msi_nonbroken is
> initialized to true in both riscv_aplic_realize() and
> riscv_imsic_realize().
>
> Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v1)
>
> hw/intc/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-07 10:03 ` [PATCH v2 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-07 10:03 ` [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
` (14 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Wilfred Mallawa, Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-riscv
Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest build")
the IBEX PLIC model was replaced with the SiFive PLIC model in the
'opentitan' machine but we forgot the add the dependency there.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 167dc4cca6..1e4b58024f 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -19,6 +19,7 @@ config MICROCHIP_PFSOC
config OPENTITAN
bool
select IBEX
+ select SIFIVE_PLIC
select UNIMP
config SHAKTI_C
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-07 10:03 ` [PATCH v2 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-07 10:03 ` [PATCH v2 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-08 10:40 ` Philippe Mathieu-Daudé
2022-12-08 22:45 ` Wilfred Mallawa
2022-12-07 10:03 ` [PATCH v2 05/16] hw/riscv: spike: Remove misleading comments Bin Meng
` (13 subsequent siblings)
16 siblings, 2 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/riscv/Kconfig | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 1e4b58024f..4550b3b938 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -4,6 +4,8 @@ config RISCV_NUMA
config IBEX
bool
+# RISC-V machines in alphabetical order
+
config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
@@ -22,13 +24,6 @@ config OPENTITAN
select SIFIVE_PLIC
select UNIMP
-config SHAKTI_C
- bool
- select UNIMP
- select SHAKTI_UART
- select RISCV_ACLINT
- select SIFIVE_PLIC
-
config RISCV_VIRT
bool
imply PCI_DEVICES
@@ -50,6 +45,13 @@ config RISCV_VIRT
select FW_CFG_DMA
select PLATFORM_BUS
+config SHAKTI_C
+ bool
+ select RISCV_ACLINT
+ select SHAKTI_UART
+ select SIFIVE_PLIC
+ select UNIMP
+
config SIFIVE_E
bool
select RISCV_ACLINT
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order
2022-12-07 10:03 ` [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
@ 2022-12-08 10:40 ` Philippe Mathieu-Daudé
2022-12-08 22:45 ` Wilfred Mallawa
1 sibling, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-12-08 10:40 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
On 7/12/22 11:03, Bin Meng wrote:
> SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v1)
>
> hw/riscv/Kconfig | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order
2022-12-07 10:03 ` [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
2022-12-08 10:40 ` Philippe Mathieu-Daudé
@ 2022-12-08 22:45 ` Wilfred Mallawa
1 sibling, 0 replies; 24+ messages in thread
From: Wilfred Mallawa @ 2022-12-08 22:45 UTC (permalink / raw)
To: bmeng@tinylab.org, qemu-devel@nongnu.org
Cc: bin.meng@windriver.com, palmer@dabbelt.com, Alistair Francis,
qemu-riscv@nongnu.org
On Wed, 2022-12-07 at 18:03 +0800, Bin Meng wrote:
> SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Wilfred
> ---
>
> (no changes since v1)
>
> hw/riscv/Kconfig | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 1e4b58024f..4550b3b938 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -4,6 +4,8 @@ config RISCV_NUMA
> config IBEX
> bool
>
> +# RISC-V machines in alphabetical order
> +
> config MICROCHIP_PFSOC
> bool
> select CADENCE_SDHCI
> @@ -22,13 +24,6 @@ config OPENTITAN
> select SIFIVE_PLIC
> select UNIMP
>
> -config SHAKTI_C
> - bool
> - select UNIMP
> - select SHAKTI_UART
> - select RISCV_ACLINT
> - select SIFIVE_PLIC
> -
> config RISCV_VIRT
> bool
> imply PCI_DEVICES
> @@ -50,6 +45,13 @@ config RISCV_VIRT
> select FW_CFG_DMA
> select PLATFORM_BUS
>
> +config SHAKTI_C
> + bool
> + select RISCV_ACLINT
> + select SHAKTI_UART
> + select SIFIVE_PLIC
> + select UNIMP
> +
> config SIFIVE_E
> bool
> select RISCV_ACLINT
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 05/16] hw/riscv: spike: Remove misleading comments
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (2 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-07 10:03 ` [PATCH v2 06/16] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
` (12 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Wilfred Mallawa, Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-riscv
PLIC is not included in the 'spike' machine.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/riscv/spike.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 1e1d752c00..13946acf0d 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -8,7 +8,6 @@
*
* 0) HTIF Console and Poweroff
* 1) CLINT (Timer and IPI)
- * 2) PLIC (Platform Level Interrupt Controller)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 06/16] hw/intc: sifive_plic: Drop PLICMode_H
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (3 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 05/16] hw/riscv: spike: Remove misleading comments Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-07 10:03 ` [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
` (11 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Wilfred Mallawa, Alistair Francis, Alistair Francis, Bin Meng,
Palmer Dabbelt, qemu-riscv
H-mode has been removed since priv spec 1.10. Drop it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/intc/sifive_plic.h | 1 -
hw/intc/sifive_plic.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
index 134cf39a96..d3f45ec248 100644
--- a/include/hw/intc/sifive_plic.h
+++ b/include/hw/intc/sifive_plic.h
@@ -33,7 +33,6 @@ DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
typedef enum PLICMode {
PLICMode_U,
PLICMode_S,
- PLICMode_H,
PLICMode_M
} PLICMode;
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 0c7696520d..936dcf74bc 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -42,7 +42,6 @@ static PLICMode char_to_mode(char c)
switch (c) {
case 'U': return PLICMode_U;
case 'S': return PLICMode_S;
- case 'H': return PLICMode_H;
case 'M': return PLICMode_M;
default:
error_report("plic: invalid mode '%c'", c);
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (4 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 06/16] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-07 10:03 ` [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Bin Meng
` (10 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-riscv
At present the PLIC config parser can only handle legal config string
like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is
given the parser won't get the correct configuration.
This commit improves the config parser to make it more robust.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/intc/sifive_plic.c | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 936dcf74bc..c9af94a888 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -290,7 +290,7 @@ static void sifive_plic_reset(DeviceState *dev)
*/
static void parse_hart_config(SiFivePLICState *plic)
{
- int addrid, hartid, modes;
+ int addrid, hartid, modes, m;
const char *p;
char c;
@@ -299,11 +299,13 @@ static void parse_hart_config(SiFivePLICState *plic)
p = plic->hart_config;
while ((c = *p++)) {
if (c == ',') {
- addrid += ctpop8(modes);
- modes = 0;
- hartid++;
+ if (modes) {
+ addrid += ctpop8(modes);
+ hartid++;
+ modes = 0;
+ }
} else {
- int m = 1 << char_to_mode(c);
+ m = 1 << char_to_mode(c);
if (modes == (modes | m)) {
error_report("plic: duplicate mode '%c' in config: %s",
c, plic->hart_config);
@@ -314,8 +316,9 @@ static void parse_hart_config(SiFivePLICState *plic)
}
if (modes) {
addrid += ctpop8(modes);
+ hartid++;
+ modes = 0;
}
- hartid++;
plic->num_addrs = addrid;
plic->num_harts = hartid;
@@ -326,11 +329,16 @@ static void parse_hart_config(SiFivePLICState *plic)
p = plic->hart_config;
while ((c = *p++)) {
if (c == ',') {
- hartid++;
+ if (modes) {
+ hartid++;
+ modes = 0;
+ }
} else {
+ m = char_to_mode(c);
plic->addr_config[addrid].addrid = addrid;
plic->addr_config[addrid].hartid = hartid;
- plic->addr_config[addrid].mode = char_to_mode(c);
+ plic->addr_config[addrid].mode = m;
+ modes |= (1 << m);
addrid++;
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (5 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-08 4:18 ` Alistair Francis
2022-12-08 10:40 ` Philippe Mathieu-Daudé
2022-12-07 10:03 ` [PATCH v2 09/16] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
` (9 subsequent siblings)
16 siblings, 2 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
The realize() callback has an errp for us to propagate the error up.
While we are here, corret the wrong multi-line comment format.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
Changes in v2:
- new patch: "hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()"
hw/intc/sifive_plic.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index c9af94a888..9cb4c6d6d4 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -379,7 +379,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
- /* We can't allow the supervisor to control SEIP as this would allow the
+ /*
+ * We can't allow the supervisor to control SEIP as this would allow the
* supervisor to clear a pending external interrupt which will result in
* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
* hardware controlled when a PLIC is attached.
@@ -387,8 +388,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
for (i = 0; i < s->num_harts; i++) {
RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
- error_report("SEIP already claimed");
- exit(1);
+ error_setg(errp, "SEIP already claimed");
+ return;
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
2022-12-07 10:03 ` [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Bin Meng
@ 2022-12-08 4:18 ` Alistair Francis
2022-12-08 10:40 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2022-12-08 4:18 UTC (permalink / raw)
To: Bin Meng; +Cc: qemu-devel, Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-riscv
On Wed, Dec 7, 2022 at 8:06 PM Bin Meng <bmeng@tinylab.org> wrote:
>
> The realize() callback has an errp for us to propagate the error up.
> While we are here, corret the wrong multi-line comment format.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v2:
> - new patch: "hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()"
>
> hw/intc/sifive_plic.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index c9af94a888..9cb4c6d6d4 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -379,7 +379,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
> qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
>
> - /* We can't allow the supervisor to control SEIP as this would allow the
> + /*
> + * We can't allow the supervisor to control SEIP as this would allow the
> * supervisor to clear a pending external interrupt which will result in
> * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
> * hardware controlled when a PLIC is attached.
> @@ -387,8 +388,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> for (i = 0; i < s->num_harts; i++) {
> RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
> if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
> - error_report("SEIP already claimed");
> - exit(1);
> + error_setg(errp, "SEIP already claimed");
> + return;
> }
> }
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
2022-12-07 10:03 ` [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Bin Meng
2022-12-08 4:18 ` Alistair Francis
@ 2022-12-08 10:40 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-12-08 10:40 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
On 7/12/22 11:03, Bin Meng wrote:
> The realize() callback has an errp for us to propagate the error up.
> While we are here, corret the wrong multi-line comment format.
Typo "correct"
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
>
> ---
>
> Changes in v2:
> - new patch: "hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()"
>
> hw/intc/sifive_plic.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 09/16] hw/intc: sifive_plic: Update "num-sources" property default value
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (6 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-07 10:03 ` [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
` (8 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-riscv
At present the default value of "num-sources" property is zero,
which does not make a lot of sense, as in sifive_plic_realize()
we see s->bitfield_words is calculated by:
s->bitfield_words = (s->num_sources + 31) >> 5;
if the we don't configure "num-sources" property its default value
zero makes s->bitfield_words zero too, which isn't true because
interrupt source 0 still occupies one word.
Let's change the default value to 1 meaning that only interrupt
source 0 is supported by default and a sanity check in realize().
While we are here, add a comment to describe the exact meaning of
this property that the number should include interrupt source 0.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v2:
- use error_setg() to propagate the error up via errp instead
hw/intc/sifive_plic.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 9cb4c6d6d4..1edeb1e1ed 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -363,6 +363,11 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
parse_hart_config(s);
+ if (!s->num_sources) {
+ error_setg(errp, "plic: invalid number of interrupt sources");
+ return;
+ }
+
s->bitfield_words = (s->num_sources + 31) >> 5;
s->num_enables = s->bitfield_words * s->num_addrs;
s->source_priority = g_new0(uint32_t, s->num_sources);
@@ -420,7 +425,8 @@ static const VMStateDescription vmstate_sifive_plic = {
static Property sifive_plic_properties[] = {
DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
- DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
+ /* number of interrupt sources including interrupt source 0 */
+ DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (7 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 09/16] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-07 10:03 ` [PATCH v2 11/16] hw/riscv: sifive_e: " Bin Meng
` (7 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Wilfred Mallawa, Alistair Francis, Conor Dooley, Bin Meng,
Palmer Dabbelt, qemu-riscv
Per chapter 6.5.2 in [1], the number of interupt sources including
interrupt source 0 should be 187.
[1] PolarFire SoC MSS TRM:
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf
Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
(no changes since v1)
include/hw/riscv/microchip_pfsoc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 69a686b54a..577efad0c4 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -153,7 +153,7 @@ enum {
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
-#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
+#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (8 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-07 10:03 ` [PATCH v2 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
` (6 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Wilfred Mallawa, Alistair Francis, Alistair Francis, Bin Meng,
Palmer Dabbelt, qemu-riscv
Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
supports 52 interrupt sources while G000 supports 51 interrupt sources.
We use the value of G002 and G003, so it is 53 (including source 0).
[1] G000 manual:
https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_fe310-g000-manual-v3p2.pdf
[2] G002 manual:
https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_fe310-g002-v1p5.pdf
[3] G003 manual:
https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf
Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/riscv/sifive_e.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index d738745925..9e58247fd8 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -82,7 +82,12 @@ enum {
};
#define SIFIVE_E_PLIC_HART_CONFIG "M"
-#define SIFIVE_E_PLIC_NUM_SOURCES 127
+/*
+ * Freedom E310 G002 and G003 supports 52 interrupt sources while
+ * Freedom E310 G000 supports 51 interrupt sources. We use the value
+ * of G002 and G003, so it is 53 (including interrupt source 0).
+ */
+#define SIFIVE_E_PLIC_NUM_SOURCES 53
#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (9 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 11/16] hw/riscv: sifive_e: " Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-07 10:03 ` [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
` (5 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Wilfred Mallawa, Alistair Francis, Alistair Francis, Bin Meng,
Palmer Dabbelt, qemu-riscv
At present magic number is used to create "riscv,ndev" property
in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
is used to instantiate the PLIC model instead.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/riscv/sifive_u.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b139824aab..b40a4767e2 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -287,7 +287,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_DEV_PLIC].base,
0x0, memmap[SIFIVE_U_DEV_PLIC].size);
- qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
+ qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
+ SIFIVE_U_PLIC_NUM_SOURCES - 1);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(cells);
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (10 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-07 10:03 ` [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
` (4 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine")
changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES
should include interrupt source 0 but "riscv,ndev" does not.
While we are here, we also fix the comments of platform bus irq range
which is now "64 to 96", but should be "64 to 95", introduced since
commit 1832b7cb3f64 ("hw/riscv: virt: Create a platform bus").
Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/riscv/virt.h | 5 ++---
hw/riscv/virt.c | 3 ++-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 62513e075c..e1ce0048af 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -87,14 +87,13 @@ enum {
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
PCIE_IRQ = 0x20, /* 32 to 35 */
- VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
- VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
+ VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
};
#define VIRT_PLATFORM_BUS_NUM_IRQS 32
#define VIRT_IRQCHIP_NUM_MSIS 255
-#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
+#define VIRT_IRQCHIP_NUM_SOURCES 96
#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6cf9355b99..94ff2a1584 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -468,7 +468,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
- qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
+ VIRT_IRQCHIP_NUM_SOURCES - 1);
riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
plic_phandles[socket]);
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (11 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-08 22:49 ` Wilfred Mallawa
2022-12-07 10:03 ` [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
` (3 subsequent siblings)
16 siblings, 1 reply; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, Alistair Francis, Bin Meng, Palmer Dabbelt,
Vijai Kumar K, qemu-riscv
At present the SiFive PLIC model "priority-base" expects interrupt
priority register base starting from source 1 instead source 0,
that's why on most platforms "priority-base" is set to 0x04 except
'opentitan' machine. 'opentitan' should have set "priority-base"
to 0x04 too.
Note the irq number calculation in sifive_plic_{read,write} is
correct as the codes make up for the irq number by adding 1.
Let's simply update "priority-base" to start from interrupt source
0 and add a comment to make it crystal clear.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/riscv/microchip_pfsoc.h | 2 +-
include/hw/riscv/shakti_c.h | 2 +-
include/hw/riscv/sifive_e.h | 2 +-
include/hw/riscv/sifive_u.h | 2 +-
include/hw/riscv/virt.h | 2 +-
hw/intc/sifive_plic.c | 5 +++--
6 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 577efad0c4..e65ffeb02d 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -155,7 +155,7 @@ enum {
#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
-#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
+#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00
#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
index daf0aae13f..539fe1156d 100644
--- a/include/hw/riscv/shakti_c.h
+++ b/include/hw/riscv/shakti_c.h
@@ -65,7 +65,7 @@ enum {
#define SHAKTI_C_PLIC_NUM_SOURCES 28
/* Excluding Priority 0 */
#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
-#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
+#define SHAKTI_C_PLIC_PRIORITY_BASE 0x00
#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 9e58247fd8..b824a79e2d 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -89,7 +89,7 @@ enum {
*/
#define SIFIVE_E_PLIC_NUM_SOURCES 53
#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
-#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
+#define SIFIVE_E_PLIC_PRIORITY_BASE 0x00
#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
#define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
#define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 8f63a183c4..e680d61ece 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -158,7 +158,7 @@ enum {
#define SIFIVE_U_PLIC_NUM_SOURCES 54
#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
-#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
+#define SIFIVE_U_PLIC_PRIORITY_BASE 0x00
#define SIFIVE_U_PLIC_PENDING_BASE 0x1000
#define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
#define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e1ce0048af..3407c9e8dd 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -98,7 +98,7 @@ enum {
#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
-#define VIRT_PLIC_PRIORITY_BASE 0x04
+#define VIRT_PLIC_PRIORITY_BASE 0x00
#define VIRT_PLIC_PENDING_BASE 0x1000
#define VIRT_PLIC_ENABLE_BASE 0x2000
#define VIRT_PLIC_ENABLE_STRIDE 0x80
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 1edeb1e1ed..1a792cc3f5 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -140,7 +140,7 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
SiFivePLICState *plic = opaque;
if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
- uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
+ uint32_t irq = (addr - plic->priority_base) >> 2;
return plic->source_priority[irq];
} else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) {
@@ -187,7 +187,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
SiFivePLICState *plic = opaque;
if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
- uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
+ uint32_t irq = (addr - plic->priority_base) >> 2;
if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
/*
@@ -428,6 +428,7 @@ static Property sifive_plic_properties[] = {
/* number of interrupt sources including interrupt source 0 */
DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
+ /* interrupt priority register base starting from source 0 */
DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
2022-12-07 10:03 ` [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
@ 2022-12-08 22:49 ` Wilfred Mallawa
0 siblings, 0 replies; 24+ messages in thread
From: Wilfred Mallawa @ 2022-12-08 22:49 UTC (permalink / raw)
To: bmeng@tinylab.org, qemu-devel@nongnu.org
Cc: bin.meng@windriver.com, palmer@dabbelt.com, Alistair Francis,
qemu-riscv@nongnu.org, vijai@behindbytes.com
On Wed, 2022-12-07 at 18:03 +0800, Bin Meng wrote:
> At present the SiFive PLIC model "priority-base" expects interrupt
> priority register base starting from source 1 instead source 0,
> that's why on most platforms "priority-base" is set to 0x04 except
> 'opentitan' machine. 'opentitan' should have set "priority-base"
> to 0x04 too.
>
> Note the irq number calculation in sifive_plic_{read,write} is
> correct as the codes make up for the irq number by adding 1.
>
> Let's simply update "priority-base" to start from interrupt source
> 0 and add a comment to make it crystal clear.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Wilfred
> ---
>
> (no changes since v1)
>
> include/hw/riscv/microchip_pfsoc.h | 2 +-
> include/hw/riscv/shakti_c.h | 2 +-
> include/hw/riscv/sifive_e.h | 2 +-
> include/hw/riscv/sifive_u.h | 2 +-
> include/hw/riscv/virt.h | 2 +-
> hw/intc/sifive_plic.c | 5 +++--
> 6 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/include/hw/riscv/microchip_pfsoc.h
> b/include/hw/riscv/microchip_pfsoc.h
> index 577efad0c4..e65ffeb02d 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -155,7 +155,7 @@ enum {
>
> #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187
> #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
> -#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
> +#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00
> #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
> #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
> #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
> diff --git a/include/hw/riscv/shakti_c.h
> b/include/hw/riscv/shakti_c.h
> index daf0aae13f..539fe1156d 100644
> --- a/include/hw/riscv/shakti_c.h
> +++ b/include/hw/riscv/shakti_c.h
> @@ -65,7 +65,7 @@ enum {
> #define SHAKTI_C_PLIC_NUM_SOURCES 28
> /* Excluding Priority 0 */
> #define SHAKTI_C_PLIC_NUM_PRIORITIES 2
> -#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
> +#define SHAKTI_C_PLIC_PRIORITY_BASE 0x00
> #define SHAKTI_C_PLIC_PENDING_BASE 0x1000
> #define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
> #define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
> diff --git a/include/hw/riscv/sifive_e.h
> b/include/hw/riscv/sifive_e.h
> index 9e58247fd8..b824a79e2d 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -89,7 +89,7 @@ enum {
> */
> #define SIFIVE_E_PLIC_NUM_SOURCES 53
> #define SIFIVE_E_PLIC_NUM_PRIORITIES 7
> -#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
> +#define SIFIVE_E_PLIC_PRIORITY_BASE 0x00
> #define SIFIVE_E_PLIC_PENDING_BASE 0x1000
> #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
> #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
> diff --git a/include/hw/riscv/sifive_u.h
> b/include/hw/riscv/sifive_u.h
> index 8f63a183c4..e680d61ece 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -158,7 +158,7 @@ enum {
>
> #define SIFIVE_U_PLIC_NUM_SOURCES 54
> #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
> -#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
> +#define SIFIVE_U_PLIC_PRIORITY_BASE 0x00
> #define SIFIVE_U_PLIC_PENDING_BASE 0x1000
> #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
> #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index e1ce0048af..3407c9e8dd 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -98,7 +98,7 @@ enum {
> #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
> #define VIRT_IRQCHIP_MAX_GUESTS ((1U <<
> VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
>
> -#define VIRT_PLIC_PRIORITY_BASE 0x04
> +#define VIRT_PLIC_PRIORITY_BASE 0x00
> #define VIRT_PLIC_PENDING_BASE 0x1000
> #define VIRT_PLIC_ENABLE_BASE 0x2000
> #define VIRT_PLIC_ENABLE_STRIDE 0x80
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 1edeb1e1ed..1a792cc3f5 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -140,7 +140,7 @@ static uint64_t sifive_plic_read(void *opaque,
> hwaddr addr, unsigned size)
> SiFivePLICState *plic = opaque;
>
> if (addr_between(addr, plic->priority_base, plic->num_sources <<
> 2)) {
> - uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
> + uint32_t irq = (addr - plic->priority_base) >> 2;
>
> return plic->source_priority[irq];
> } else if (addr_between(addr, plic->pending_base, plic-
> >num_sources >> 3)) {
> @@ -187,7 +187,7 @@ static void sifive_plic_write(void *opaque,
> hwaddr addr, uint64_t value,
> SiFivePLICState *plic = opaque;
>
> if (addr_between(addr, plic->priority_base, plic->num_sources <<
> 2)) {
> - uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
> + uint32_t irq = (addr - plic->priority_base) >> 2;
>
> if (((plic->num_priorities + 1) & plic->num_priorities) ==
> 0) {
> /*
> @@ -428,6 +428,7 @@ static Property sifive_plic_properties[] = {
> /* number of interrupt sources including interrupt source 0 */
> DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources,
> 1),
> DEFINE_PROP_UINT32("num-priorities", SiFivePLICState,
> num_priorities, 0),
> + /* interrupt priority register base starting from source 0 */
> DEFINE_PROP_UINT32("priority-base", SiFivePLICState,
> priority_base, 0),
> DEFINE_PROP_UINT32("pending-base", SiFivePLICState,
> pending_base, 0),
> DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base,
> 0),
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (12 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-07 10:03 ` [PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
` (2 subsequent siblings)
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Wilfred Mallawa, Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-riscv
"hartid-base" and "priority-base" are zero by default. There is no
need to initialize them to zero again.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
(no changes since v1)
hw/riscv/opentitan.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 78f895d773..85ffdac5be 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -173,10 +173,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
/* PLIC */
qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
- qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
- qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range check
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (13 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
@ 2022-12-07 10:03 ` Bin Meng
2022-12-08 10:38 ` [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Philippe Mathieu-Daudé
2022-12-08 22:46 ` Wilfred Mallawa
16 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2022-12-07 10:03 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-riscv
The pending register upper limit is currently set to
plic->num_sources >> 3, which is wrong, e.g.: considering
plic->num_sources is 7, the upper limit becomes 0 which fails
the range check if reading the pending register at pending_base.
Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/intc/sifive_plic.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 1a792cc3f5..5522ede2cf 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -143,7 +143,8 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
uint32_t irq = (addr - plic->priority_base) >> 2;
return plic->source_priority[irq];
- } else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) {
+ } else if (addr_between(addr, plic->pending_base,
+ (plic->num_sources + 31) >> 3)) {
uint32_t word = (addr - plic->pending_base) >> 2;
return plic->pending[word];
@@ -202,7 +203,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
sifive_plic_update(plic);
}
} else if (addr_between(addr, plic->pending_base,
- plic->num_sources >> 3)) {
+ (plic->num_sources + 31) >> 3)) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid pending write: 0x%" HWADDR_PRIx "",
__func__, addr);
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (14 preceding siblings ...)
2022-12-07 10:03 ` [PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
@ 2022-12-08 10:38 ` Philippe Mathieu-Daudé
2022-12-08 22:46 ` Wilfred Mallawa
16 siblings, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-12-08 10:38 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
On 7/12/22 11:03, Bin Meng wrote:
> hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
> controllers regardless of how MSI is implemented. msi_nonbroken is
> initialized to true in sifive_plic_realize().
>
> Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from
> RISC-V machines.
12 years with this inverted logic... *sigh*.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v1)
>
> hw/intc/Kconfig | 1 +
> hw/riscv/Kconfig | 5 -----
> 2 files changed, 1 insertion(+), 5 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
2022-12-07 10:03 [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
` (15 preceding siblings ...)
2022-12-08 10:38 ` [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Philippe Mathieu-Daudé
@ 2022-12-08 22:46 ` Wilfred Mallawa
16 siblings, 0 replies; 24+ messages in thread
From: Wilfred Mallawa @ 2022-12-08 22:46 UTC (permalink / raw)
To: bmeng@tinylab.org, qemu-devel@nongnu.org
Cc: bin.meng@windriver.com, palmer@dabbelt.com, Alistair Francis,
qemu-riscv@nongnu.org
On Wed, 2022-12-07 at 18:03 +0800, Bin Meng wrote:
> hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
> controllers regardless of how MSI is implemented. msi_nonbroken is
> initialized to true in sifive_plic_realize().
>
> Let SIFIVE_PLIC select MSI_NONBROKEN and drop the selection from
> RISC-V machines.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Wilfred
> ---
>
> (no changes since v1)
>
> hw/intc/Kconfig | 1 +
> hw/riscv/Kconfig | 5 -----
> 2 files changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index ecd2883ceb..1d4573e803 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -78,6 +78,7 @@ config RISCV_IMSIC
>
> config SIFIVE_PLIC
> bool
> + select MSI_NONBROKEN
>
> config GOLDFISH_PIC
> bool
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 79ff61c464..167dc4cca6 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -11,7 +11,6 @@ config MICROCHIP_PFSOC
> select MCHP_PFSOC_IOSCB
> select MCHP_PFSOC_MMUART
> select MCHP_PFSOC_SYSREG
> - select MSI_NONBROKEN
> select RISCV_ACLINT
> select SIFIVE_PDMA
> select SIFIVE_PLIC
> @@ -37,7 +36,6 @@ config RISCV_VIRT
> imply TPM_TIS_SYSBUS
> select RISCV_NUMA
> select GOLDFISH_RTC
> - select MSI_NONBROKEN
> select PCI
> select PCI_EXPRESS_GENERIC_BRIDGE
> select PFLASH_CFI01
> @@ -53,7 +51,6 @@ config RISCV_VIRT
>
> config SIFIVE_E
> bool
> - select MSI_NONBROKEN
> select RISCV_ACLINT
> select SIFIVE_GPIO
> select SIFIVE_PLIC
> @@ -64,7 +61,6 @@ config SIFIVE_E
> config SIFIVE_U
> bool
> select CADENCE
> - select MSI_NONBROKEN
> select RISCV_ACLINT
> select SIFIVE_GPIO
> select SIFIVE_PDMA
> @@ -82,6 +78,5 @@ config SPIKE
> bool
> select RISCV_NUMA
> select HTIF
> - select MSI_NONBROKEN
> select RISCV_ACLINT
> select SIFIVE_PLIC
^ permalink raw reply [flat|nested] 24+ messages in thread