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Mon, 24 Mar 2025 18:37:21 -0700 (PDT) Received: from [192.168.1.67] ([38.39.164.180]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73906158ef2sm9090422b3a.141.2025.03.24.18.37.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Mar 2025 18:37:21 -0700 (PDT) Message-ID: Date: Mon, 24 Mar 2025 18:10:37 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 08/17] target/avr: Add offset-io cpu property Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org References: <20250323173730.3213964-1-richard.henderson@linaro.org> <20250323173730.3213964-9-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250323173730.3213964-9-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/23/25 10:37, Richard Henderson wrote: > Communicate the offset of io within the first page between the > board, the cpu, and the translator. So far this is always 0. > This will be used to optimize memory layout. > > Signed-off-by: Richard Henderson > --- > target/avr/cpu.h | 2 ++ > hw/avr/atmega.c | 2 ++ > target/avr/cpu.c | 1 + > target/avr/translate.c | 2 ++ > 4 files changed, 7 insertions(+) > > diff --git a/target/avr/cpu.h b/target/avr/cpu.h > index be27b0152b..0f5e1a53bc 100644 > --- a/target/avr/cpu.h > +++ b/target/avr/cpu.h > @@ -148,6 +148,8 @@ struct ArchCPU { > > /* Initial value of stack pointer */ > uint32_t init_sp; > + /* Offset of the beginning of I/O within the first page. */ > + uint32_t offset_io; > }; > > /** > diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c > index f6844bf118..273582b8af 100644 > --- a/hw/avr/atmega.c > +++ b/hw/avr/atmega.c > @@ -236,6 +236,8 @@ static void atmega_realize(DeviceState *dev, Error **errp) > > object_property_set_uint(OBJECT(&s->cpu), "init-sp", > mc->io_size + mc->sram_size - 1, &error_abort); > + object_property_set_uint(OBJECT(&s->cpu), "offset-io", > + 0, &error_abort); > > qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); > cpudev = DEVICE(&s->cpu); > diff --git a/target/avr/cpu.c b/target/avr/cpu.c > index 0b14b36c17..080f6f30d3 100644 > --- a/target/avr/cpu.c > +++ b/target/avr/cpu.c > @@ -169,6 +169,7 @@ static void avr_cpu_initfn(Object *obj) > > static const Property avr_cpu_properties[] = { > DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0), > + DEFINE_PROP_UINT32("offset-io", AVRCPU, offset_io, 0), > }; > > static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) > diff --git a/target/avr/translate.c b/target/avr/translate.c > index 0490936cd5..e9fef1aaad 100644 > --- a/target/avr/translate.c > +++ b/target/avr/translate.c > @@ -92,6 +92,7 @@ struct DisasContext { > > /* Routine used to access memory */ > int memidx; > + uint32_t offset_io; > > /* > * some AVR instructions can make the following instruction to be skipped > @@ -2664,6 +2665,7 @@ static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->cs = cs; > ctx->env = cpu_env(cs); > ctx->npc = ctx->base.pc_first / 2; > + ctx->offset_io = env_archcpu(ctx->env)->offset_io; > > ctx->skip_cond = TCG_COND_NEVER; > if (tb_flags & TB_FLAGS_SKIP) { Reviewed-by: Pierrick Bouvier