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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac10d1ccesm17400135ad.20.2024.06.28.09.01.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Jun 2024 09:01:58 -0700 (PDT) Message-ID: Date: Fri, 28 Jun 2024 09:01:56 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/9] target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20240628142347.1283015-1-peter.maydell@linaro.org> <20240628142347.1283015-5-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240628142347.1283015-5-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/28/24 07:23, Peter Maydell wrote: > To support FPSR and FPCR bits that don't exist in the AArch32 FPSCR > view of floating point control and status (such as the FEAT_AFP ones), > we need to make sure those bits can be migrated. This commit allows > that, whilst maintaining backwards and forwards migration compatibility > for CPUs where there are no such bits: > > On sending: > * If either the FPCR or the FPSR include set bits that are not > visible in the AArch32 FPSCR view of floating point control/status > then we send the FPCR and FPSR as two separate fields in a new > cpu/vfp/fpcr_fpsr subsection, and we send a 0 for the old > FPSCR field in cpu/vfp > * Otherwise, we don't send the fpcr_fpsr subsection, and we send > an FPSCR-format value in cpu/vfp as we did previously > > On receiving: > * if we see a non-zero FPSCR field, that is the right information > * if we see a fpcr_fpsr subsection then that has the information > * if we see neither, then FPSCR/FPCR/FPSR are all zero on the source; > cpu_pre_load() ensures the CPU state defaults to that > * if we see both, then the migration source is buggy or malicious; > either the fpcr_fpsr or the FPSCR will "win" depending which > is first in the migration stream; we don't care which that is > > We make the new FPCR and FPSR on-the-wire data be 64 bits, because > architecturally these registers are that wide, and this avoids the > need to engage in further migration-compatibility contortions in > future if some new architecture revision defines bits in the high > half of either register. > > (We won't ever send the new migration subsection until we add support > for a CPU feature which enables setting overlapping FPCR bits, like > FEAT_AFP.) > > Signed-off-by: Peter Maydell > --- > target/arm/machine.c | 134 ++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 132 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson Not ideal, as vfp_get_{fpcr,fpsr} are called 3 or 4 times during migration. But unless we have separate 'fp*r_migrate' fields in cpu state, initialized in pre_save, there's no getting around it. And I suppose migration isn't exactly performance critical. r~