* [PATCH v3 0/5] Generate x86 cpu features
@ 2024-02-06 13:47 Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 1/5] target/i386: Split out feature_word_info Tim Wiederhake
` (6 more replies)
0 siblings, 7 replies; 10+ messages in thread
From: Tim Wiederhake @ 2024-02-06 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Philippe Mathieu-Daudé, Paolo Bonzini,
Daniel P . Berrangé, Michael S . Tsirkin, Tim Wiederhake
Synchronizing the list of cpu features and models with qemu is a recurring
task in libvirt. For x86, this is done by reading qom-list-properties for
max-x86_64-cpu and manually filtering out everthing that does not look like
a feature name, as well as parsing target/i386/cpu.c for cpu models.
This is a flawed, tedious and error-prone procedure. Ideally, qemu
and libvirt would query a common source for cpu feature and model
related information. Meanwhile, converting this information into an easier
to parse format would help libvirt a lot.
This patch series converts the cpu feature information present in
target/i386/cpu.c (`feature_word_info`) into a yaml file and adds a
script to generate the c code from this data.
v1: https://lists.nongnu.org/archive/html/qemu-devel/2023-08/msg02005.html
v2: https://lists.nongnu.org/archive/html/qemu-devel/2023-09/msg01773.html
Changes since v2:
* Rebased on top of current master
* Removed all "drive-by" changes to feature names ("vmx-ept-uc", "vmx-ept-wb",
"kvmclock", "vmx-invept-single-context", and
"vmx-invept-single-context-noglobals") as these needed further discussion.
* Changes to the generator script reduce the changes in formatting to the
current feature_word_info even further to address the concern about code
legibility. See Patch 5, "target/i386: Generate feature_word_info.c.inc" for
all non-whitespace changes.
Tim Wiederhake (5):
target/i386: Split out feature_word_info
target/i386: Translate feature_word_info to yaml
target/i386: Remove comments from feature_word_info.c.inc
target/i386: Fix feature_word_info.c.inc formatting
target/i386: Generate feature_word_info.c.inc
target/i386/cpu.c | 679 +-------------------------
target/i386/feature_word_info.c.inc | 710 ++++++++++++++++++++++++++++
target/i386/feature_word_info.py | 71 +++
target/i386/feature_word_info.yaml | 701 +++++++++++++++++++++++++++
4 files changed, 1483 insertions(+), 678 deletions(-)
create mode 100644 target/i386/feature_word_info.c.inc
create mode 100755 target/i386/feature_word_info.py
create mode 100644 target/i386/feature_word_info.yaml
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 1/5] target/i386: Split out feature_word_info
2024-02-06 13:47 [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
@ 2024-02-06 13:47 ` Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 2/5] target/i386: Translate feature_word_info to yaml Tim Wiederhake
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Tim Wiederhake @ 2024-02-06 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Philippe Mathieu-Daudé, Paolo Bonzini,
Daniel P . Berrangé, Michael S . Tsirkin, Tim Wiederhake
The isolated part will be generated by a script.
Signed-off-by: Tim Wiederhake <twiederh@redhat.com>
---
target/i386/cpu.c | 679 +---------------------------
target/i386/feature_word_info.c.inc | 678 +++++++++++++++++++++++++++
2 files changed, 679 insertions(+), 678 deletions(-)
create mode 100644 target/i386/feature_word_info.c.inc
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ef46755a50..e87bce1970 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -763,684 +763,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
#define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \
CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES)
-FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
- [FEAT_1_EDX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "fpu", "vme", "de", "pse",
- "tsc", "msr", "pae", "mce",
- "cx8", "apic", NULL, "sep",
- "mtrr", "pge", "mca", "cmov",
- "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
- NULL, "ds" /* Intel dts */, "acpi", "mmx",
- "fxsr", "sse", "sse2", "ss",
- "ht" /* Intel htt */, "tm", "ia64", "pbe",
- },
- .cpuid = {.eax = 1, .reg = R_EDX, },
- .tcg_features = TCG_FEATURES,
- .no_autoenable_flags = CPUID_HT,
- },
- [FEAT_1_ECX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
- "ds-cpl", "vmx", "smx", "est",
- "tm2", "ssse3", "cid", NULL,
- "fma", "cx16", "xtpr", "pdcm",
- NULL, "pcid", "dca", "sse4.1",
- "sse4.2", "x2apic", "movbe", "popcnt",
- "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
- "avx", "f16c", "rdrand", "hypervisor",
- },
- .cpuid = { .eax = 1, .reg = R_ECX, },
- .tcg_features = TCG_EXT_FEATURES,
- },
- /* Feature names that are already defined on feature_name[] but
- * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
- * names on feat_names below. They are copied automatically
- * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
- */
- [FEAT_8000_0001_EDX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
- NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
- NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
- NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
- NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
- "nx", NULL, "mmxext", NULL /* mmx */,
- NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
- NULL, "lm", "3dnowext", "3dnow",
- },
- .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
- .tcg_features = TCG_EXT2_FEATURES,
- },
- [FEAT_8000_0001_ECX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "lahf-lm", "cmp-legacy", "svm", "extapic",
- "cr8legacy", "abm", "sse4a", "misalignsse",
- "3dnowprefetch", "osvw", "ibs", "xop",
- "skinit", "wdt", NULL, "lwp",
- "fma4", "tce", NULL, "nodeid-msr",
- NULL, "tbm", "topoext", "perfctr-core",
- "perfctr-nb", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
- .tcg_features = TCG_EXT3_FEATURES,
- /*
- * TOPOEXT is always allowed but can't be enabled blindly by
- * "-cpu host", as it requires consistent cache topology info
- * to be provided so it doesn't confuse guests.
- */
- .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
- },
- [FEAT_C000_0001_EDX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, "xstore", "xstore-en",
- NULL, NULL, "xcrypt", "xcrypt-en",
- "ace2", "ace2-en", "phe", "phe-en",
- "pmm", "pmm-en", NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
- .tcg_features = TCG_EXT4_FEATURES,
- },
- [FEAT_KVM] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
- "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
- NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
- "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- "kvmclock-stable-bit", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
- .tcg_features = TCG_KVM_FEATURES,
- },
- [FEAT_KVM_HINTS] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "kvm-hint-dedicated", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
- .tcg_features = TCG_KVM_FEATURES,
- /*
- * KVM hints aren't auto-enabled by -cpu host, they need to be
- * explicitly enabled in the command-line.
- */
- .no_autoenable_flags = ~0U,
- },
- [FEAT_SVM] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "npt", "lbrv", "svm-lock", "nrip-save",
- "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
- NULL, NULL, "pause-filter", NULL,
- "pfthreshold", "avic", NULL, "v-vmsave-vmload",
- "vgif", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, "vnmi", NULL, NULL,
- "svme-addr-chk", NULL, NULL, NULL,
- },
- .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
- .tcg_features = TCG_SVM_FEATURES,
- },
- [FEAT_7_0_EBX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "fsgsbase", "tsc-adjust", "sgx", "bmi1",
- "hle", "avx2", NULL, "smep",
- "bmi2", "erms", "invpcid", "rtm",
- NULL, NULL, "mpx", NULL,
- "avx512f", "avx512dq", "rdseed", "adx",
- "smap", "avx512ifma", "pcommit", "clflushopt",
- "clwb", "intel-pt", "avx512pf", "avx512er",
- "avx512cd", "sha-ni", "avx512bw", "avx512vl",
- },
- .cpuid = {
- .eax = 7,
- .needs_ecx = true, .ecx = 0,
- .reg = R_EBX,
- },
- .tcg_features = TCG_7_0_EBX_FEATURES,
- },
- [FEAT_7_0_ECX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, "avx512vbmi", "umip", "pku",
- NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
- "gfni", "vaes", "vpclmulqdq", "avx512vnni",
- "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
- "la57", NULL, NULL, NULL,
- NULL, NULL, "rdpid", NULL,
- "bus-lock-detect", "cldemote", NULL, "movdiri",
- "movdir64b", NULL, "sgxlc", "pks",
- },
- .cpuid = {
- .eax = 7,
- .needs_ecx = true, .ecx = 0,
- .reg = R_ECX,
- },
- .tcg_features = TCG_7_0_ECX_FEATURES,
- },
- [FEAT_7_0_EDX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
- "fsrm", NULL, NULL, NULL,
- "avx512-vp2intersect", NULL, "md-clear", NULL,
- NULL, NULL, "serialize", NULL,
- "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
- NULL, NULL, "amx-bf16", "avx512-fp16",
- "amx-tile", "amx-int8", "spec-ctrl", "stibp",
- "flush-l1d", "arch-capabilities", "core-capability", "ssbd",
- },
- .cpuid = {
- .eax = 7,
- .needs_ecx = true, .ecx = 0,
- .reg = R_EDX,
- },
- .tcg_features = TCG_7_0_EDX_FEATURES,
- },
- [FEAT_7_1_EAX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, NULL, NULL,
- "avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
- NULL, NULL, "fzrm", "fsrs",
- "fsrc", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, "amx-fp16", NULL, "avx-ifma",
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = {
- .eax = 7,
- .needs_ecx = true, .ecx = 1,
- .reg = R_EAX,
- },
- .tcg_features = TCG_7_1_EAX_FEATURES,
- },
- [FEAT_7_1_EDX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, NULL, NULL,
- "avx-vnni-int8", "avx-ne-convert", NULL, NULL,
- "amx-complex", NULL, NULL, NULL,
- NULL, NULL, "prefetchiti", NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = {
- .eax = 7,
- .needs_ecx = true, .ecx = 1,
- .reg = R_EDX,
- },
- .tcg_features = TCG_7_1_EDX_FEATURES,
- },
- [FEAT_7_2_EDX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, NULL, NULL,
- NULL, "mcdt-no", NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = {
- .eax = 7,
- .needs_ecx = true, .ecx = 2,
- .reg = R_EDX,
- },
- .tcg_features = TCG_7_2_EDX_FEATURES,
- },
- [FEAT_8000_0007_EDX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- "invtsc", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
- .tcg_features = TCG_APM_FEATURES,
- .unmigratable_flags = CPUID_APM_INVTSC,
- },
- [FEAT_8000_0008_EBX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "clzero", NULL, "xsaveerptr", NULL,
- NULL, NULL, NULL, NULL,
- NULL, "wbnoinvd", NULL, NULL,
- "ibpb", NULL, "ibrs", "amd-stibp",
- NULL, "stibp-always-on", NULL, NULL,
- NULL, NULL, NULL, NULL,
- "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
- "amd-psfd", NULL, NULL, NULL,
- },
- .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
- .tcg_features = TCG_8000_0008_EBX,
- .unmigratable_flags = 0,
- },
- [FEAT_8000_0021_EAX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
- NULL, NULL, "null-sel-clr-base", NULL,
- "auto-ibrs", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = { .eax = 0x80000021, .reg = R_EAX, },
- .tcg_features = 0,
- .unmigratable_flags = 0,
- },
- [FEAT_XSAVE] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "xsaveopt", "xsavec", "xgetbv1", "xsaves",
- "xfd", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = {
- .eax = 0xd,
- .needs_ecx = true, .ecx = 1,
- .reg = R_EAX,
- },
- .tcg_features = TCG_XSAVE_FEATURES,
- },
- [FEAT_XSAVE_XSS_LO] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = {
- .eax = 0xD,
- .needs_ecx = true,
- .ecx = 1,
- .reg = R_ECX,
- },
- },
- [FEAT_XSAVE_XSS_HI] = {
- .type = CPUID_FEATURE_WORD,
- .cpuid = {
- .eax = 0xD,
- .needs_ecx = true,
- .ecx = 1,
- .reg = R_EDX
- },
- },
- [FEAT_6_EAX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, "arat", NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = { .eax = 6, .reg = R_EAX, },
- .tcg_features = TCG_6_EAX_FEATURES,
- },
- [FEAT_XSAVE_XCR0_LO] = {
- .type = CPUID_FEATURE_WORD,
- .cpuid = {
- .eax = 0xD,
- .needs_ecx = true, .ecx = 0,
- .reg = R_EAX,
- },
- .tcg_features = ~0U,
- .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
- XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
- XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
- XSTATE_PKRU_MASK,
- },
- [FEAT_XSAVE_XCR0_HI] = {
- .type = CPUID_FEATURE_WORD,
- .cpuid = {
- .eax = 0xD,
- .needs_ecx = true, .ecx = 0,
- .reg = R_EDX,
- },
- .tcg_features = ~0U,
- },
- /*Below are MSR exposed features*/
- [FEAT_ARCH_CAPABILITIES] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
- "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
- "taa-no", NULL, NULL, NULL,
- NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
- NULL, "fb-clear", NULL, NULL,
- NULL, NULL, NULL, NULL,
- "pbrsb-no", NULL, "gds-no", NULL,
- NULL, NULL, NULL, NULL,
- },
- .msr = {
- .index = MSR_IA32_ARCH_CAPABILITIES,
- },
- /*
- * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which
- * cannot be read from user mode. Therefore, it has no impact
- > on any user-mode operation, and warnings about unsupported
- * features do not matter.
- */
- .tcg_features = ~0U,
- },
- [FEAT_CORE_CAPABILITY] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, NULL, NULL,
- NULL, "split-lock-detect", NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .msr = {
- .index = MSR_IA32_CORE_CAPABILITY,
- },
- },
- [FEAT_PERF_CAPABILITIES] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, "full-width-write", NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .msr = {
- .index = MSR_IA32_PERF_CAPABILITIES,
- },
- },
-
- [FEAT_VMX_PROCBASED_CTLS] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
- NULL, NULL, NULL, "vmx-hlt-exit",
- NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
- "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
- "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
- "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
- "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
- "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
- },
- .msr = {
- .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
- }
- },
-
- [FEAT_VMX_SECONDARY_CTLS] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
- "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
- "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
- "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
- "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
- "vmx-xsaves", NULL, NULL, NULL,
- NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL,
- NULL, NULL, NULL, NULL,
- },
- .msr = {
- .index = MSR_IA32_VMX_PROCBASED_CTLS2,
- }
- },
-
- [FEAT_VMX_PINBASED_CTLS] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
- NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .msr = {
- .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
- }
- },
-
- [FEAT_VMX_EXIT_CTLS] = {
- .type = MSR_FEATURE_WORD,
- /*
- * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
- * the LM CPUID bit.
- */
- .feat_names = {
- NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
- "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
- NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
- "vmx-exit-save-efer", "vmx-exit-load-efer",
- "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
- NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
- NULL, "vmx-exit-load-pkrs", NULL, NULL,
- },
- .msr = {
- .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
- }
- },
-
- [FEAT_VMX_ENTRY_CTLS] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, "vmx-entry-noload-debugctl", NULL,
- NULL, NULL, NULL, NULL,
- NULL, "vmx-entry-ia32e-mode", NULL, NULL,
- NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
- "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
- NULL, NULL, "vmx-entry-load-pkrs", NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .msr = {
- .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
- }
- },
-
- [FEAT_VMX_MISC] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, NULL, NULL,
- NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
- "vmx-activity-wait-sipi", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
- },
- .msr = {
- .index = MSR_IA32_VMX_MISC,
- }
- },
-
- [FEAT_VMX_EPT_VPID_CAPS] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- "vmx-ept-execonly", NULL, NULL, NULL,
- NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
- "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
- NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
- NULL, NULL, NULL, NULL,
- "vmx-invvpid", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- "vmx-invvpid-single-addr", "vmx-invept-single-context",
- "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .msr = {
- .index = MSR_IA32_VMX_EPT_VPID_CAP,
- }
- },
-
- [FEAT_VMX_BASIC] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- [54] = "vmx-ins-outs",
- [55] = "vmx-true-ctls",
- [56] = "vmx-any-errcode",
- },
- .msr = {
- .index = MSR_IA32_VMX_BASIC,
- },
- /* Just to be safe - we don't support setting the MSEG version field. */
- .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
- },
-
- [FEAT_VMX_VMFUNC] = {
- .type = MSR_FEATURE_WORD,
- .feat_names = {
- [0] = "vmx-eptp-switching",
- },
- .msr = {
- .index = MSR_IA32_VMX_VMFUNC,
- }
- },
-
- [FEAT_14_0_ECX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, "intel-pt-lip",
- },
- .cpuid = {
- .eax = 0x14,
- .needs_ecx = true, .ecx = 0,
- .reg = R_ECX,
- },
- .tcg_features = TCG_14_0_ECX_FEATURES,
- },
-
- [FEAT_SGX_12_0_EAX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "sgx1", "sgx2", NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, "sgx-edeccssa",
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = {
- .eax = 0x12,
- .needs_ecx = true, .ecx = 0,
- .reg = R_EAX,
- },
- .tcg_features = TCG_SGX_12_0_EAX_FEATURES,
- },
-
- [FEAT_SGX_12_0_EBX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- "sgx-exinfo" , NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = {
- .eax = 0x12,
- .needs_ecx = true, .ecx = 0,
- .reg = R_EBX,
- },
- .tcg_features = TCG_SGX_12_0_EBX_FEATURES,
- },
-
- [FEAT_SGX_12_1_EAX] = {
- .type = CPUID_FEATURE_WORD,
- .feat_names = {
- NULL, "sgx-debug", "sgx-mode64", NULL,
- "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
- NULL, NULL, "sgx-aex-notify", NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
- },
- .cpuid = {
- .eax = 0x12,
- .needs_ecx = true, .ecx = 1,
- .reg = R_EAX,
- },
- .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
- },
-};
+#include "feature_word_info.c.inc"
typedef struct FeatureMask {
FeatureWord index;
diff --git a/target/i386/feature_word_info.c.inc b/target/i386/feature_word_info.c.inc
new file mode 100644
index 0000000000..4c6a1613ae
--- /dev/null
+++ b/target/i386/feature_word_info.c.inc
@@ -0,0 +1,678 @@
+FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
+ [FEAT_1_EDX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "fpu", "vme", "de", "pse",
+ "tsc", "msr", "pae", "mce",
+ "cx8", "apic", NULL, "sep",
+ "mtrr", "pge", "mca", "cmov",
+ "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
+ NULL, "ds" /* Intel dts */, "acpi", "mmx",
+ "fxsr", "sse", "sse2", "ss",
+ "ht" /* Intel htt */, "tm", "ia64", "pbe",
+ },
+ .cpuid = {.eax = 1, .reg = R_EDX, },
+ .tcg_features = TCG_FEATURES,
+ .no_autoenable_flags = CPUID_HT,
+ },
+ [FEAT_1_ECX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
+ "ds-cpl", "vmx", "smx", "est",
+ "tm2", "ssse3", "cid", NULL,
+ "fma", "cx16", "xtpr", "pdcm",
+ NULL, "pcid", "dca", "sse4.1",
+ "sse4.2", "x2apic", "movbe", "popcnt",
+ "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
+ "avx", "f16c", "rdrand", "hypervisor",
+ },
+ .cpuid = { .eax = 1, .reg = R_ECX, },
+ .tcg_features = TCG_EXT_FEATURES,
+ },
+ /* Feature names that are already defined on feature_name[] but
+ * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
+ * names on feat_names below. They are copied automatically
+ * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
+ */
+ [FEAT_8000_0001_EDX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
+ NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
+ NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
+ NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
+ NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
+ "nx", NULL, "mmxext", NULL /* mmx */,
+ NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
+ NULL, "lm", "3dnowext", "3dnow",
+ },
+ .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
+ .tcg_features = TCG_EXT2_FEATURES,
+ },
+ [FEAT_8000_0001_ECX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "lahf-lm", "cmp-legacy", "svm", "extapic",
+ "cr8legacy", "abm", "sse4a", "misalignsse",
+ "3dnowprefetch", "osvw", "ibs", "xop",
+ "skinit", "wdt", NULL, "lwp",
+ "fma4", "tce", NULL, "nodeid-msr",
+ NULL, "tbm", "topoext", "perfctr-core",
+ "perfctr-nb", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
+ .tcg_features = TCG_EXT3_FEATURES,
+ /*
+ * TOPOEXT is always allowed but can't be enabled blindly by
+ * "-cpu host", as it requires consistent cache topology info
+ * to be provided so it doesn't confuse guests.
+ */
+ .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
+ },
+ [FEAT_C000_0001_EDX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, "xstore", "xstore-en",
+ NULL, NULL, "xcrypt", "xcrypt-en",
+ "ace2", "ace2-en", "phe", "phe-en",
+ "pmm", "pmm-en", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
+ .tcg_features = TCG_EXT4_FEATURES,
+ },
+ [FEAT_KVM] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
+ "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
+ NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
+ "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ "kvmclock-stable-bit", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
+ .tcg_features = TCG_KVM_FEATURES,
+ },
+ [FEAT_KVM_HINTS] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "kvm-hint-dedicated", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
+ .tcg_features = TCG_KVM_FEATURES,
+ /*
+ * KVM hints aren't auto-enabled by -cpu host, they need to be
+ * explicitly enabled in the command-line.
+ */
+ .no_autoenable_flags = ~0U,
+ },
+ [FEAT_SVM] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "npt", "lbrv", "svm-lock", "nrip-save",
+ "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
+ NULL, NULL, "pause-filter", NULL,
+ "pfthreshold", "avic", NULL, "v-vmsave-vmload",
+ "vgif", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, "vnmi", NULL, NULL,
+ "svme-addr-chk", NULL, NULL, NULL,
+ },
+ .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
+ .tcg_features = TCG_SVM_FEATURES,
+ },
+ [FEAT_7_0_EBX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "fsgsbase", "tsc-adjust", "sgx", "bmi1",
+ "hle", "avx2", NULL, "smep",
+ "bmi2", "erms", "invpcid", "rtm",
+ NULL, NULL, "mpx", NULL,
+ "avx512f", "avx512dq", "rdseed", "adx",
+ "smap", "avx512ifma", "pcommit", "clflushopt",
+ "clwb", "intel-pt", "avx512pf", "avx512er",
+ "avx512cd", "sha-ni", "avx512bw", "avx512vl",
+ },
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EBX,
+ },
+ .tcg_features = TCG_7_0_EBX_FEATURES,
+ },
+ [FEAT_7_0_ECX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, "avx512vbmi", "umip", "pku",
+ NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
+ "gfni", "vaes", "vpclmulqdq", "avx512vnni",
+ "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
+ "la57", NULL, NULL, NULL,
+ NULL, NULL, "rdpid", NULL,
+ "bus-lock-detect", "cldemote", NULL, "movdiri",
+ "movdir64b", NULL, "sgxlc", "pks",
+ },
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_ECX,
+ },
+ .tcg_features = TCG_7_0_ECX_FEATURES,
+ },
+ [FEAT_7_0_EDX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
+ "fsrm", NULL, NULL, NULL,
+ "avx512-vp2intersect", NULL, "md-clear", NULL,
+ NULL, NULL, "serialize", NULL,
+ "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
+ NULL, NULL, "amx-bf16", "avx512-fp16",
+ "amx-tile", "amx-int8", "spec-ctrl", "stibp",
+ "flush-l1d", "arch-capabilities", "core-capability", "ssbd",
+ },
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EDX,
+ },
+ .tcg_features = TCG_7_0_EDX_FEATURES,
+ },
+ [FEAT_7_1_EAX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ "avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
+ NULL, NULL, "fzrm", "fsrs",
+ "fsrc", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, "amx-fp16", NULL, "avx-ifma",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_EAX,
+ },
+ .tcg_features = TCG_7_1_EAX_FEATURES,
+ },
+ [FEAT_7_1_EDX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ "avx-vnni-int8", "avx-ne-convert", NULL, NULL,
+ "amx-complex", NULL, NULL, NULL,
+ NULL, NULL, "prefetchiti", NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_EDX,
+ },
+ .tcg_features = TCG_7_1_EDX_FEATURES,
+ },
+ [FEAT_7_2_EDX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, "mcdt-no", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 2,
+ .reg = R_EDX,
+ },
+ .tcg_features = TCG_7_2_EDX_FEATURES,
+ },
+ [FEAT_8000_0007_EDX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ "invtsc", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
+ .tcg_features = TCG_APM_FEATURES,
+ .unmigratable_flags = CPUID_APM_INVTSC,
+ },
+ [FEAT_8000_0008_EBX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "clzero", NULL, "xsaveerptr", NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, "wbnoinvd", NULL, NULL,
+ "ibpb", NULL, "ibrs", "amd-stibp",
+ NULL, "stibp-always-on", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
+ "amd-psfd", NULL, NULL, NULL,
+ },
+ .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
+ .tcg_features = TCG_8000_0008_EBX,
+ .unmigratable_flags = 0,
+ },
+ [FEAT_8000_0021_EAX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
+ NULL, NULL, "null-sel-clr-base", NULL,
+ "auto-ibrs", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = { .eax = 0x80000021, .reg = R_EAX, },
+ .tcg_features = 0,
+ .unmigratable_flags = 0,
+ },
+ [FEAT_XSAVE] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "xsaveopt", "xsavec", "xgetbv1", "xsaves",
+ "xfd", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 0xd,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_EAX,
+ },
+ .tcg_features = TCG_XSAVE_FEATURES,
+ },
+ [FEAT_XSAVE_XSS_LO] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 0xD,
+ .needs_ecx = true,
+ .ecx = 1,
+ .reg = R_ECX,
+ },
+ },
+ [FEAT_XSAVE_XSS_HI] = {
+ .type = CPUID_FEATURE_WORD,
+ .cpuid = {
+ .eax = 0xD,
+ .needs_ecx = true,
+ .ecx = 1,
+ .reg = R_EDX
+ },
+ },
+ [FEAT_6_EAX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, "arat", NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = { .eax = 6, .reg = R_EAX, },
+ .tcg_features = TCG_6_EAX_FEATURES,
+ },
+ [FEAT_XSAVE_XCR0_LO] = {
+ .type = CPUID_FEATURE_WORD,
+ .cpuid = {
+ .eax = 0xD,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EAX,
+ },
+ .tcg_features = ~0U,
+ .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
+ XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
+ XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
+ XSTATE_PKRU_MASK,
+ },
+ [FEAT_XSAVE_XCR0_HI] = {
+ .type = CPUID_FEATURE_WORD,
+ .cpuid = {
+ .eax = 0xD,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EDX,
+ },
+ .tcg_features = ~0U,
+ },
+ /*Below are MSR exposed features*/
+ [FEAT_ARCH_CAPABILITIES] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
+ "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
+ "taa-no", NULL, NULL, NULL,
+ NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
+ NULL, "fb-clear", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ "pbrsb-no", NULL, "gds-no", NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_ARCH_CAPABILITIES,
+ },
+ /*
+ * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which
+ * cannot be read from user mode. Therefore, it has no impact
+ > on any user-mode operation, and warnings about unsupported
+ * features do not matter.
+ */
+ .tcg_features = ~0U,
+ },
+ [FEAT_CORE_CAPABILITY] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, "split-lock-detect", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_CORE_CAPABILITY,
+ },
+ },
+ [FEAT_PERF_CAPABILITIES] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, "full-width-write", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_PERF_CAPABILITIES,
+ },
+ },
+
+ [FEAT_VMX_PROCBASED_CTLS] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
+ NULL, NULL, NULL, "vmx-hlt-exit",
+ NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
+ "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
+ "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
+ "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
+ "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
+ "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
+ },
+ .msr = {
+ .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
+ }
+ },
+
+ [FEAT_VMX_SECONDARY_CTLS] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
+ "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
+ "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
+ "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
+ "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
+ "vmx-xsaves", NULL, NULL, NULL,
+ NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_VMX_PROCBASED_CTLS2,
+ }
+ },
+
+ [FEAT_VMX_PINBASED_CTLS] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
+ NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
+ }
+ },
+
+ [FEAT_VMX_EXIT_CTLS] = {
+ .type = MSR_FEATURE_WORD,
+ /*
+ * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
+ * the LM CPUID bit.
+ */
+ .feat_names = {
+ NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
+ "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
+ NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
+ "vmx-exit-save-efer", "vmx-exit-load-efer",
+ "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
+ NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
+ NULL, "vmx-exit-load-pkrs", NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
+ }
+ },
+
+ [FEAT_VMX_ENTRY_CTLS] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, "vmx-entry-noload-debugctl", NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, "vmx-entry-ia32e-mode", NULL, NULL,
+ NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
+ "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
+ NULL, NULL, "vmx-entry-load-pkrs", NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
+ }
+ },
+
+ [FEAT_VMX_MISC] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
+ "vmx-activity-wait-sipi", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_VMX_MISC,
+ }
+ },
+
+ [FEAT_VMX_EPT_VPID_CAPS] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ "vmx-ept-execonly", NULL, NULL, NULL,
+ NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
+ "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
+ NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
+ NULL, NULL, NULL, NULL,
+ "vmx-invvpid", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ "vmx-invvpid-single-addr", "vmx-invept-single-context",
+ "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_VMX_EPT_VPID_CAP,
+ }
+ },
+
+ [FEAT_VMX_BASIC] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ [54] = "vmx-ins-outs",
+ [55] = "vmx-true-ctls",
+ [56] = "vmx-any-errcode",
+ },
+ .msr = {
+ .index = MSR_IA32_VMX_BASIC,
+ },
+ /* Just to be safe - we don't support setting the MSEG version field. */
+ .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
+ },
+
+ [FEAT_VMX_VMFUNC] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ [0] = "vmx-eptp-switching",
+ },
+ .msr = {
+ .index = MSR_IA32_VMX_VMFUNC,
+ }
+ },
+
+ [FEAT_14_0_ECX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, "intel-pt-lip",
+ },
+ .cpuid = {
+ .eax = 0x14,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_ECX,
+ },
+ .tcg_features = TCG_14_0_ECX_FEATURES,
+ },
+
+ [FEAT_SGX_12_0_EAX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "sgx1", "sgx2", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, "sgx-edeccssa",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 0x12,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EAX,
+ },
+ .tcg_features = TCG_SGX_12_0_EAX_FEATURES,
+ },
+
+ [FEAT_SGX_12_0_EBX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "sgx-exinfo" , NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 0x12,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EBX,
+ },
+ .tcg_features = TCG_SGX_12_0_EBX_FEATURES,
+ },
+
+ [FEAT_SGX_12_1_EAX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, "sgx-debug", "sgx-mode64", NULL,
+ "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
+ NULL, NULL, "sgx-aex-notify", NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 0x12,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_EAX,
+ },
+ .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
+ },
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 2/5] target/i386: Translate feature_word_info to yaml
2024-02-06 13:47 [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 1/5] target/i386: Split out feature_word_info Tim Wiederhake
@ 2024-02-06 13:47 ` Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 3/5] target/i386: Remove comments from feature_word_info.c.inc Tim Wiederhake
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Tim Wiederhake @ 2024-02-06 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Philippe Mathieu-Daudé, Paolo Bonzini,
Daniel P . Berrangé, Michael S . Tsirkin, Tim Wiederhake
This is the data file that will be used to generate the C code.
All information, including the comments, is preserved.
Signed-off-by: Tim Wiederhake <twiederh@redhat.com>
---
target/i386/feature_word_info.yaml | 699 +++++++++++++++++++++++++++++
1 file changed, 699 insertions(+)
create mode 100644 target/i386/feature_word_info.yaml
diff --git a/target/i386/feature_word_info.yaml b/target/i386/feature_word_info.yaml
new file mode 100644
index 0000000000..7a8ca3f051
--- /dev/null
+++ b/target/i386/feature_word_info.yaml
@@ -0,0 +1,699 @@
+- index: FEAT_1_EDX
+ cpuid:
+ eax: '1'
+ reg: R_EDX
+ feat_names:
+ 0: fpu
+ 1: vme
+ 2: de
+ 3: pse
+ 4: tsc
+ 5: msr
+ 6: pae
+ 7: mce
+ 8: cx8
+ 9: apic
+ 11: sep
+ 12: mtrr
+ 13: pge
+ 14: mca
+ 15: cmov
+ 16: pat
+ 17: pse36
+ 18: pn # Intel psn
+ 19: clflush # Intel clfsh
+ 21: ds # Intel dts
+ 22: acpi
+ 23: mmx
+ 24: fxsr
+ 25: sse
+ 26: sse2
+ 27: ss
+ 28: ht # Intel htt
+ 29: tm
+ 30: ia64
+ 31: pbe
+ no_autoenable_flags: CPUID_HT
+ tcg_features: TCG_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_1_ECX
+ cpuid:
+ eax: '1'
+ reg: R_ECX
+ feat_names:
+ 0: pni # Intel,AMD sse3
+ 1: pclmulqdq
+ 2: dtes64
+ 3: monitor
+ 4: ds-cpl
+ 5: vmx
+ 6: smx
+ 7: est
+ 8: tm2
+ 9: ssse3
+ 10: cid
+ 12: fma
+ 13: cx16
+ 14: xtpr
+ 15: pdcm
+ 17: pcid
+ 18: dca
+ 19: sse4.1
+ 20: sse4.2
+ 21: x2apic
+ 22: movbe
+ 23: popcnt
+ 24: tsc-deadline
+ 25: aes
+ 26: xsave
+ # 27: osxsave
+ 28: avx
+ 29: f16c
+ 30: rdrand
+ 31: hypervisor
+ tcg_features: TCG_EXT_FEATURES
+ type: CPUID_FEATURE_WORD
+
+# Feature names that are already defined on feature_name[] but are set on
+# CPUID[8000_0001].EDX on AMD CPUs don't have their names on feat_names below.
+# They are copied automatically to features[FEAT_8000_0001_EDX] if and only if
+# CPU vendor is AMD.
+- index: FEAT_8000_0001_EDX
+ cpuid:
+ eax: '0x80000001'
+ reg: R_EDX
+ feat_names:
+ # 0: fpu
+ # 1: vme
+ # 2: de
+ # 3: pse
+ # 4: tsc
+ # 5: msr
+ # 6: pae
+ # 7: mce
+ # 8: cx8
+ # 9: apic
+ 11: syscall
+ # 12: mtrr
+ # 13: pge
+ # 14: mca
+ # 15: cmov
+ # 16: pat
+ # 17: pse36
+ # 19: Linux mp
+ 20: nx
+ 22: mmxext
+ # 23: mmx
+ # 24: fxsr
+ 25: fxsr-opt
+ 26: pdpe1gb
+ 27: rdtscp
+ 29: lm
+ 30: 3dnowext
+ 31: 3dnow
+ tcg_features: TCG_EXT2_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_8000_0001_ECX
+ cpuid:
+ eax: '0x80000001'
+ reg: R_ECX
+ feat_names:
+ 0: lahf-lm
+ 1: cmp-legacy
+ 2: svm
+ 3: extapic
+ 4: cr8legacy
+ 5: abm
+ 6: sse4a
+ 7: misalignsse
+ 8: 3dnowprefetch
+ 9: osvw
+ 10: ibs
+ 11: xop
+ 12: skinit
+ 13: wdt
+ 15: lwp
+ 16: fma4
+ 17: tce
+ 19: nodeid-msr
+ 21: tbm
+ 22: topoext
+ 23: perfctr-core
+ 24: perfctr-nb
+ # TOPOEXT is always allowed but can't be enabled blindly by "-cpu host", as
+ # it requires consistent cache topology info to be provided so it doesn't
+ # confuse guests.
+ no_autoenable_flags: CPUID_EXT3_TOPOEXT
+ tcg_features: TCG_EXT3_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_C000_0001_EDX
+ cpuid:
+ eax: '0xC0000001'
+ reg: R_EDX
+ feat_names:
+ 2: xstore
+ 3: xstore-en
+ 6: xcrypt
+ 7: xcrypt-en
+ 8: ace2
+ 9: ace2-en
+ 10: phe
+ 11: phe-en
+ 12: pmm
+ 13: pmm-en
+ tcg_features: TCG_EXT4_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_KVM
+ cpuid:
+ eax: KVM_CPUID_FEATURES
+ reg: R_EAX
+ feat_names:
+ 0: kvmclock
+ 1: kvm-nopiodelay
+ 2: kvm-mmu
+ 3: kvmclock
+ 4: kvm-asyncpf
+ 5: kvm-steal-time
+ 6: kvm-pv-eoi
+ 7: kvm-pv-unhalt
+ 9: kvm-pv-tlb-flush
+ 11: kvm-pv-ipi
+ 12: kvm-poll-control
+ 13: kvm-pv-sched-yield
+ 14: kvm-asyncpf-int
+ 15: kvm-msi-ext-dest-id
+ 24: kvmclock-stable-bit
+ tcg_features: TCG_KVM_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_KVM_HINTS
+ cpuid:
+ eax: KVM_CPUID_FEATURES
+ reg: R_EDX
+ feat_names:
+ 0: kvm-hint-dedicated
+ # KVM hints aren't auto-enabled by -cpu host, they need to be explicitly
+ # enabled in the command-line.
+ no_autoenable_flags: ~0U
+ tcg_features: TCG_KVM_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_SVM
+ cpuid:
+ eax: '0x8000000A'
+ reg: R_EDX
+ feat_names:
+ 0: npt
+ 1: lbrv
+ 2: svm-lock
+ 3: nrip-save
+ 4: tsc-scale
+ 5: vmcb-clean
+ 6: flushbyasid
+ 7: decodeassists
+ 10: pause-filter
+ 12: pfthreshold
+ 13: avic
+ 15: v-vmsave-vmload
+ 16: vgif
+ 25: vnmi
+ 28: svme-addr-chk
+ tcg_features: TCG_SVM_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_7_0_EBX
+ cpuid:
+ eax: '7'
+ ecx: '0'
+ needs_ecx: 'true'
+ reg: R_EBX
+ feat_names:
+ 0: fsgsbase
+ 1: tsc-adjust
+ 2: sgx
+ 3: bmi1
+ 4: hle
+ 5: avx2
+ 7: smep
+ 8: bmi2
+ 9: erms
+ 10: invpcid
+ 11: rtm
+ 14: mpx
+ 16: avx512f
+ 17: avx512dq
+ 18: rdseed
+ 19: adx
+ 20: smap
+ 21: avx512ifma
+ 22: pcommit
+ 23: clflushopt
+ 24: clwb
+ 25: intel-pt
+ 26: avx512pf
+ 27: avx512er
+ 28: avx512cd
+ 29: sha-ni
+ 30: avx512bw
+ 31: avx512vl
+ tcg_features: TCG_7_0_EBX_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_7_0_ECX
+ cpuid:
+ eax: '7'
+ ecx: '0'
+ needs_ecx: 'true'
+ reg: R_ECX
+ feat_names:
+ 1: avx512vbmi
+ 2: umip
+ 3: pku
+ # 4: ospke
+ 5: waitpkg
+ 6: avx512vbmi2
+ 8: gfni
+ 9: vaes
+ 10: vpclmulqdq
+ 11: avx512vnni
+ 12: avx512bitalg
+ 14: avx512-vpopcntdq
+ 16: la57
+ 22: rdpid
+ 24: bus-lock-detect
+ 25: cldemote
+ 27: movdiri
+ 28: movdir64b
+ 30: sgxlc
+ 31: pks
+ tcg_features: TCG_7_0_ECX_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_7_0_EDX
+ cpuid:
+ eax: '7'
+ ecx: '0'
+ needs_ecx: 'true'
+ reg: R_EDX
+ feat_names:
+ 2: avx512-4vnniw
+ 3: avx512-4fmaps
+ 4: fsrm
+ 8: avx512-vp2intersect
+ 10: md-clear
+ 14: serialize
+ 16: tsx-ldtrk
+ # 18: pconfig
+ 19: arch-lbr
+ 22: amx-bf16
+ 23: avx512-fp16
+ 24: amx-tile
+ 25: amx-int8
+ 26: spec-ctrl
+ 27: stibp
+ 28: flush-l1d
+ 29: arch-capabilities
+ 30: core-capability
+ 31: ssbd
+ tcg_features: TCG_7_0_EDX_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_7_1_EAX
+ cpuid:
+ eax: '7'
+ ecx: '1'
+ needs_ecx: 'true'
+ reg: R_EAX
+ feat_names:
+ 4: avx-vnni
+ 5: avx512-bf16
+ 7: cmpccxadd
+ 10: fzrm
+ 11: fsrs
+ 12: fsrc
+ 21: amx-fp16
+ 23: avx-ifma
+ tcg_features: TCG_7_1_EAX_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_7_1_EDX
+ cpuid:
+ eax: '7'
+ ecx: '1'
+ needs_ecx: 'true'
+ reg: R_EDX
+ feat_names:
+ 4: avx-vnni-int8
+ 5: avx-ne-convert
+ 8: amx-complex
+ 14: prefetchiti
+ tcg_features: TCG_7_1_EDX_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_7_2_EDX
+ cpuid:
+ eax: '7'
+ ecx: '2'
+ needs_ecx: 'true'
+ reg: R_EDX
+ feat_names:
+ 5: mcdt-no
+ tcg_features: TCG_7_2_EDX_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_8000_0007_EDX
+ cpuid:
+ eax: '0x80000007'
+ reg: R_EDX
+ feat_names:
+ 8: invtsc
+ tcg_features: TCG_APM_FEATURES
+ type: CPUID_FEATURE_WORD
+ unmigratable_flags: CPUID_APM_INVTSC
+
+- index: FEAT_8000_0008_EBX
+ cpuid:
+ eax: '0x80000008'
+ reg: R_EBX
+ feat_names:
+ 0: clzero
+ 2: xsaveerptr
+ 9: wbnoinvd
+ 12: ibpb
+ 14: ibrs
+ 15: amd-stibp
+ 17: stibp-always-on
+ 24: amd-ssbd
+ 25: virt-ssbd
+ 26: amd-no-ssb
+ 28: amd-psfd
+ tcg_features: TCG_8000_0008_EBX
+ type: CPUID_FEATURE_WORD
+ unmigratable_flags: '0'
+
+- index: FEAT_8000_0021_EAX
+ cpuid:
+ eax: '0x80000021'
+ reg: R_EAX
+ feat_names:
+ 0: no-nested-data-bp
+ 2: lfence-always-serializing
+ 6: null-sel-clr-base
+ 8: auto-ibrs
+ tcg_features: '0'
+ type: CPUID_FEATURE_WORD
+ unmigratable_flags: '0'
+
+- index: FEAT_XSAVE
+ cpuid:
+ eax: '0xd'
+ ecx: '1'
+ needs_ecx: 'true'
+ reg: R_EAX
+ feat_names:
+ 0: xsaveopt
+ 1: xsavec
+ 2: xgetbv1
+ 3: xsaves
+ 4: xfd
+ tcg_features: TCG_XSAVE_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_XSAVE_XSS_LO
+ cpuid:
+ eax: '0xD'
+ ecx: '1'
+ needs_ecx: 'true'
+ reg: R_ECX
+ feat_names: {}
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_XSAVE_XSS_HI
+ cpuid:
+ eax: '0xD'
+ ecx: '1'
+ needs_ecx: 'true'
+ reg: R_EDX
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_6_EAX
+ cpuid:
+ eax: '6'
+ reg: R_EAX
+ feat_names:
+ 2: arat
+ tcg_features: TCG_6_EAX_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_XSAVE_XCR0_LO
+ cpuid:
+ eax: '0xD'
+ ecx: '0'
+ needs_ecx: 'true'
+ reg: R_EAX
+ migratable_flags: |-
+ XSTATE_FP_MASK | XSTATE_SSE_MASK |
+ XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
+ XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
+ XSTATE_PKRU_MASK
+ tcg_features: ~0U
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_XSAVE_XCR0_HI
+ cpuid:
+ eax: '0xD'
+ ecx: '0'
+ needs_ecx: 'true'
+ reg: R_EDX
+ tcg_features: ~0U
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_ARCH_CAPABILITIES
+ msr: MSR_IA32_ARCH_CAPABILITIES
+ feat_names:
+ 0: rdctl-no
+ 1: ibrs-all
+ 2: rsba
+ 3: skip-l1dfl-vmentry
+ 4: ssb-no
+ 5: mds-no
+ 6: pschange-mc-no
+ 7: tsx-ctrl
+ 8: taa-no
+ 13: sbdr-ssdp-no
+ 14: fbsdp-no
+ 15: psdp-no
+ 17: fb-clear
+ 24: pbrsb-no
+ 26: gds-no
+ # FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which cannot be read
+ # from user mode. Therefore, it has no impact on any user-mode operation,
+ # and warnings about unsupported features do not matter.
+ tcg_features: ~0U
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_CORE_CAPABILITY
+ msr: MSR_IA32_CORE_CAPABILITY
+ feat_names:
+ 5: split-lock-detect
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_PERF_CAPABILITIES
+ msr: MSR_IA32_PERF_CAPABILITIES
+ feat_names:
+ 13: full-width-write
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_VMX_PROCBASED_CTLS
+ msr: MSR_IA32_VMX_TRUE_PROCBASED_CTLS
+ feat_names:
+ 2: vmx-vintr-pending
+ 3: vmx-tsc-offset
+ 7: vmx-hlt-exit
+ 9: vmx-invlpg-exit
+ 10: vmx-mwait-exit
+ 11: vmx-rdpmc-exit
+ 12: vmx-rdtsc-exit
+ 15: vmx-cr3-load-noexit
+ 16: vmx-cr3-store-noexit
+ 19: vmx-cr8-load-exit
+ 20: vmx-cr8-store-exit
+ 21: vmx-flexpriority
+ 22: vmx-vnmi-pending
+ 23: vmx-movdr-exit
+ 24: vmx-io-exit
+ 25: vmx-io-bitmap
+ 27: vmx-mtf
+ 28: vmx-msr-bitmap
+ 29: vmx-monitor-exit
+ 30: vmx-pause-exit
+ 31: vmx-secondary-ctls
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_VMX_SECONDARY_CTLS
+ msr: MSR_IA32_VMX_PROCBASED_CTLS2
+ feat_names:
+ 0: vmx-apicv-xapic
+ 1: vmx-ept
+ 2: vmx-desc-exit
+ 3: vmx-rdtscp-exit
+ 4: vmx-apicv-x2apic
+ 5: vmx-vpid
+ 6: vmx-wbinvd-exit
+ 7: vmx-unrestricted-guest
+ 8: vmx-apicv-register
+ 9: vmx-apicv-vid
+ 10: vmx-ple
+ 11: vmx-rdrand-exit
+ 12: vmx-invpcid-exit
+ 13: vmx-vmfunc
+ 14: vmx-shadow-vmcs
+ 15: vmx-encls-exit
+ 16: vmx-rdseed-exit
+ 17: vmx-pml
+ 20: vmx-xsaves
+ 25: vmx-tsc-scaling
+ 26: vmx-enable-user-wait-pause
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_VMX_PINBASED_CTLS
+ msr: MSR_IA32_VMX_TRUE_PINBASED_CTLS
+ feat_names:
+ 0: vmx-intr-exit
+ 3: vmx-nmi-exit
+ 5: vmx-vnmi
+ 6: vmx-preemption-timer
+ 7: vmx-posted-intr
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_VMX_EXIT_CTLS
+ msr: MSR_IA32_VMX_TRUE_EXIT_CTLS
+ feat_names:
+ 2: vmx-exit-nosave-debugctl
+ #9: VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from the LM CPUID bit.
+ 12: vmx-exit-load-perf-global-ctrl
+ 15: vmx-exit-ack-intr
+ 18: vmx-exit-save-pat
+ 19: vmx-exit-load-pat
+ 20: vmx-exit-save-efer
+ 21: vmx-exit-load-efer
+ 22: vmx-exit-save-preemption-timer
+ 23: vmx-exit-clear-bndcfgs
+ 25: vmx-exit-clear-rtit-ctl
+ 29: vmx-exit-load-pkrs
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_VMX_ENTRY_CTLS
+ msr: MSR_IA32_VMX_TRUE_ENTRY_CTLS
+ feat_names:
+ 2: vmx-entry-noload-debugctl
+ 9: vmx-entry-ia32e-mode
+ 13: vmx-entry-load-perf-global-ctrl
+ 14: vmx-entry-load-pat
+ 15: vmx-entry-load-efer
+ 16: vmx-entry-load-bndcfgs
+ 18: vmx-entry-load-rtit-ctl
+ 22: vmx-entry-load-pkrs
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_VMX_MISC
+ msr: MSR_IA32_VMX_MISC
+ feat_names:
+ 5: vmx-store-lma
+ 6: vmx-activity-hlt
+ 7: vmx-activity-shutdown
+ 8: vmx-activity-wait-sipi
+ 29: vmx-vmwrite-vmexit-fields
+ 30: vmx-zero-len-inject
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_VMX_EPT_VPID_CAPS
+ msr: MSR_IA32_VMX_EPT_VPID_CAP
+ feat_names:
+ 0: vmx-ept-execonly
+ 6: vmx-page-walk-4
+ 7: vmx-page-walk-5
+ 16: vmx-ept-2mb
+ 17: vmx-ept-1gb
+ 20: vmx-invept
+ 21: vmx-eptad
+ 22: vmx-ept-advanced-exitinfo
+ 25: vmx-invept-single-context
+ 26: vmx-invept-all-context
+ 32: vmx-invvpid
+ 40: vmx-invvpid-single-addr
+ 41: vmx-invept-single-context
+ 42: vmx-invvpid-all-context
+ 43: vmx-invept-single-context-noglobals
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_VMX_BASIC
+ msr: MSR_IA32_VMX_BASIC
+ feat_names:
+ 54: vmx-ins-outs
+ 55: vmx-true-ctls
+ 56: vmx-any-errcode
+ # Just to be safe - we don't support setting the MSEG version field.
+ no_autoenable_flags: MSR_VMX_BASIC_DUAL_MONITOR
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_VMX_VMFUNC
+ msr: MSR_IA32_VMX_VMFUNC
+ feat_names:
+ 0: vmx-eptp-switching
+ type: MSR_FEATURE_WORD
+
+- index: FEAT_14_0_ECX
+ cpuid:
+ eax: '0x14'
+ ecx: '0'
+ needs_ecx: 'true'
+ reg: R_ECX
+ feat_names:
+ 31: intel-pt-lip
+ tcg_features: TCG_14_0_ECX_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_SGX_12_0_EAX
+ cpuid:
+ eax: '0x12'
+ ecx: '0'
+ needs_ecx: 'true'
+ reg: R_EAX
+ feat_names:
+ 0: sgx1
+ 1: sgx2
+ 11: sgx-edeccssa
+ tcg_features: TCG_SGX_12_0_EAX_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_SGX_12_0_EBX
+ cpuid:
+ eax: '0x12'
+ ecx: '0'
+ needs_ecx: 'true'
+ reg: R_EBX
+ feat_names:
+ 0: sgx-exinfo
+ tcg_features: TCG_SGX_12_0_EBX_FEATURES
+ type: CPUID_FEATURE_WORD
+
+- index: FEAT_SGX_12_1_EAX
+ cpuid:
+ eax: '0x12'
+ ecx: '1'
+ needs_ecx: 'true'
+ reg: R_EAX
+ feat_names:
+ 1: sgx-debug
+ 2: sgx-mode64
+ 4: sgx-provisionkey
+ 5: sgx-tokenkey
+ 7: sgx-kss
+ 10: sgx-aex-notify
+ tcg_features: TCG_SGX_12_1_EAX_FEATURES
+ type: CPUID_FEATURE_WORD
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 3/5] target/i386: Remove comments from feature_word_info.c.inc
2024-02-06 13:47 [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 1/5] target/i386: Split out feature_word_info Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 2/5] target/i386: Translate feature_word_info to yaml Tim Wiederhake
@ 2024-02-06 13:47 ` Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 4/5] target/i386: Fix feature_word_info.c.inc formatting Tim Wiederhake
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Tim Wiederhake @ 2024-02-06 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Philippe Mathieu-Daudé, Paolo Bonzini,
Daniel P . Berrangé, Michael S . Tsirkin, Tim Wiederhake
The comments are preserved in the yaml file.
Signed-off-by: Tim Wiederhake <twiederh@redhat.com>
---
target/i386/feature_word_info.c.inc | 56 ++++++++---------------------
1 file changed, 15 insertions(+), 41 deletions(-)
diff --git a/target/i386/feature_word_info.c.inc b/target/i386/feature_word_info.c.inc
index 4c6a1613ae..152d4b45a9 100644
--- a/target/i386/feature_word_info.c.inc
+++ b/target/i386/feature_word_info.c.inc
@@ -6,10 +6,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"tsc", "msr", "pae", "mce",
"cx8", "apic", NULL, "sep",
"mtrr", "pge", "mca", "cmov",
- "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
- NULL, "ds" /* Intel dts */, "acpi", "mmx",
+ "pat", "pse36", "pn", "clflush",
+ NULL, "ds", "acpi", "mmx",
"fxsr", "sse", "sse2", "ss",
- "ht" /* Intel htt */, "tm", "ia64", "pbe",
+ "ht", "tm", "ia64", "pbe",
},
.cpuid = {.eax = 1, .reg = R_EDX, },
.tcg_features = TCG_FEATURES,
@@ -18,33 +18,28 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_1_ECX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
- "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
+ "pni", "pclmulqdq", "dtes64", "monitor",
"ds-cpl", "vmx", "smx", "est",
"tm2", "ssse3", "cid", NULL,
"fma", "cx16", "xtpr", "pdcm",
NULL, "pcid", "dca", "sse4.1",
"sse4.2", "x2apic", "movbe", "popcnt",
- "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
+ "tsc-deadline", "aes", "xsave", NULL,
"avx", "f16c", "rdrand", "hypervisor",
},
.cpuid = { .eax = 1, .reg = R_ECX, },
.tcg_features = TCG_EXT_FEATURES,
},
- /* Feature names that are already defined on feature_name[] but
- * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
- * names on feat_names below. They are copied automatically
- * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
- */
[FEAT_8000_0001_EDX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
- NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
- NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
- NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
- NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
- NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
- "nx", NULL, "mmxext", NULL /* mmx */,
- NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, "syscall",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ "nx", NULL, "mmxext", NULL,
+ NULL, "fxsr-opt", "pdpe1gb", "rdtscp",
NULL, "lm", "3dnowext", "3dnow",
},
.cpuid = { .eax = 0x80000001, .reg = R_EDX, },
@@ -64,11 +59,6 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = { .eax = 0x80000001, .reg = R_ECX, },
.tcg_features = TCG_EXT3_FEATURES,
- /*
- * TOPOEXT is always allowed but can't be enabled blindly by
- * "-cpu host", as it requires consistent cache topology info
- * to be provided so it doesn't confuse guests.
- */
.no_autoenable_flags = CPUID_EXT3_TOPOEXT,
},
[FEAT_C000_0001_EDX] = {
@@ -115,10 +105,6 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
.tcg_features = TCG_KVM_FEATURES,
- /*
- * KVM hints aren't auto-enabled by -cpu host, they need to be
- * explicitly enabled in the command-line.
- */
.no_autoenable_flags = ~0U,
},
[FEAT_SVM] = {
@@ -159,7 +145,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, "avx512vbmi", "umip", "pku",
- NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
+ NULL, "waitpkg", "avx512vbmi2", NULL,
"gfni", "vaes", "vpclmulqdq", "avx512vnni",
"avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
"la57", NULL, NULL, NULL,
@@ -181,7 +167,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"fsrm", NULL, NULL, NULL,
"avx512-vp2intersect", NULL, "md-clear", NULL,
NULL, NULL, "serialize", NULL,
- "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
+ "tsx-ldtrk", NULL, NULL, "arch-lbr",
NULL, NULL, "amx-bf16", "avx512-fp16",
"amx-tile", "amx-int8", "spec-ctrl", "stibp",
"flush-l1d", "arch-capabilities", "core-capability", "ssbd",
@@ -382,7 +368,6 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = ~0U,
},
- /*Below are MSR exposed features*/
[FEAT_ARCH_CAPABILITIES] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
@@ -398,12 +383,6 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.msr = {
.index = MSR_IA32_ARCH_CAPABILITIES,
},
- /*
- * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which
- * cannot be read from user mode. Therefore, it has no impact
- > on any user-mode operation, and warnings about unsupported
- * features do not matter.
- */
.tcg_features = ~0U,
},
[FEAT_CORE_CAPABILITY] = {
@@ -492,14 +471,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_VMX_EXIT_CTLS] = {
.type = MSR_FEATURE_WORD,
- /*
- * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
- * the LM CPUID bit.
- */
.feat_names = {
NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
NULL, NULL, NULL, NULL,
- NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
+ NULL, NULL, NULL, NULL,
"vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
"vmx-exit-save-efer", "vmx-exit-load-efer",
@@ -582,7 +557,6 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.msr = {
.index = MSR_IA32_VMX_BASIC,
},
- /* Just to be safe - we don't support setting the MSEG version field. */
.no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
},
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 4/5] target/i386: Fix feature_word_info.c.inc formatting
2024-02-06 13:47 [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
` (2 preceding siblings ...)
2024-02-06 13:47 ` [PATCH v3 3/5] target/i386: Remove comments from feature_word_info.c.inc Tim Wiederhake
@ 2024-02-06 13:47 ` Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 5/5] target/i386: Generate feature_word_info.c.inc Tim Wiederhake
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Tim Wiederhake @ 2024-02-06 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Philippe Mathieu-Daudé, Paolo Bonzini,
Daniel P . Berrangé, Michael S . Tsirkin, Tim Wiederhake
Make the formatting of the file more regular. This reduces the
diff to the generated version.
Signed-off-by: Tim Wiederhake <twiederh@redhat.com>
---
target/i386/feature_word_info.c.inc | 136 ++++++++++++++++++----------
1 file changed, 86 insertions(+), 50 deletions(-)
diff --git a/target/i386/feature_word_info.c.inc b/target/i386/feature_word_info.c.inc
index 152d4b45a9..4beae01918 100644
--- a/target/i386/feature_word_info.c.inc
+++ b/target/i386/feature_word_info.c.inc
@@ -11,7 +11,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"fxsr", "sse", "sse2", "ss",
"ht", "tm", "ia64", "pbe",
},
- .cpuid = {.eax = 1, .reg = R_EDX, },
+ .cpuid = {
+ .eax = 1,
+ .reg = R_EDX,
+ },
.tcg_features = TCG_FEATURES,
.no_autoenable_flags = CPUID_HT,
},
@@ -27,7 +30,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"tsc-deadline", "aes", "xsave", NULL,
"avx", "f16c", "rdrand", "hypervisor",
},
- .cpuid = { .eax = 1, .reg = R_ECX, },
+ .cpuid = {
+ .eax = 1,
+ .reg = R_ECX,
+ },
.tcg_features = TCG_EXT_FEATURES,
},
[FEAT_8000_0001_EDX] = {
@@ -42,7 +48,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, "fxsr-opt", "pdpe1gb", "rdtscp",
NULL, "lm", "3dnowext", "3dnow",
},
- .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
+ .cpuid = {
+ .eax = 0x80000001,
+ .reg = R_EDX,
+ },
.tcg_features = TCG_EXT2_FEATURES,
},
[FEAT_8000_0001_ECX] = {
@@ -57,7 +66,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"perfctr-nb", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
+ .cpuid = {
+ .eax = 0x80000001,
+ .reg = R_ECX,
+ },
.tcg_features = TCG_EXT3_FEATURES,
.no_autoenable_flags = CPUID_EXT3_TOPOEXT,
},
@@ -73,7 +85,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
+ .cpuid = {
+ .eax = 0xC0000001,
+ .reg = R_EDX,
+ },
.tcg_features = TCG_EXT4_FEATURES,
},
[FEAT_KVM] = {
@@ -88,7 +103,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"kvmclock-stable-bit", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
+ .cpuid = {
+ .eax = KVM_CPUID_FEATURES,
+ .reg = R_EAX,
+ },
.tcg_features = TCG_KVM_FEATURES,
},
[FEAT_KVM_HINTS] = {
@@ -103,7 +121,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
+ .cpuid = {
+ .eax = KVM_CPUID_FEATURES,
+ .reg = R_EDX,
+ },
.tcg_features = TCG_KVM_FEATURES,
.no_autoenable_flags = ~0U,
},
@@ -111,7 +132,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
"npt", "lbrv", "svm-lock", "nrip-save",
- "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
+ "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
NULL, NULL, "pause-filter", NULL,
"pfthreshold", "avic", NULL, "v-vmsave-vmload",
"vgif", NULL, NULL, NULL,
@@ -119,7 +140,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, "vnmi", NULL, NULL,
"svme-addr-chk", NULL, NULL, NULL,
},
- .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
+ .cpuid = {
+ .eax = 0x8000000A,
+ .reg = R_EDX,
+ },
.tcg_features = TCG_SVM_FEATURES,
},
[FEAT_7_0_EBX] = {
@@ -136,7 +160,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 7,
- .needs_ecx = true, .ecx = 0,
+ .needs_ecx = true,
+ .ecx = 0,
.reg = R_EBX,
},
.tcg_features = TCG_7_0_EBX_FEATURES,
@@ -155,7 +180,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 7,
- .needs_ecx = true, .ecx = 0,
+ .needs_ecx = true,
+ .ecx = 0,
.reg = R_ECX,
},
.tcg_features = TCG_7_0_ECX_FEATURES,
@@ -174,7 +200,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 7,
- .needs_ecx = true, .ecx = 0,
+ .needs_ecx = true,
+ .ecx = 0,
.reg = R_EDX,
},
.tcg_features = TCG_7_0_EDX_FEATURES,
@@ -193,7 +220,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 7,
- .needs_ecx = true, .ecx = 1,
+ .needs_ecx = true,
+ .ecx = 1,
.reg = R_EAX,
},
.tcg_features = TCG_7_1_EAX_FEATURES,
@@ -212,7 +240,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 7,
- .needs_ecx = true, .ecx = 1,
+ .needs_ecx = true,
+ .ecx = 1,
.reg = R_EDX,
},
.tcg_features = TCG_7_1_EDX_FEATURES,
@@ -231,7 +260,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 7,
- .needs_ecx = true, .ecx = 2,
+ .needs_ecx = true,
+ .ecx = 2,
.reg = R_EDX,
},
.tcg_features = TCG_7_2_EDX_FEATURES,
@@ -248,7 +278,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
+ .cpuid = {
+ .eax = 0x80000007,
+ .reg = R_EDX,
+ },
.tcg_features = TCG_APM_FEATURES,
.unmigratable_flags = CPUID_APM_INVTSC,
},
@@ -264,7 +297,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
"amd-psfd", NULL, NULL, NULL,
},
- .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
+ .cpuid = {
+ .eax = 0x80000008,
+ .reg = R_EBX,
+ },
.tcg_features = TCG_8000_0008_EBX,
.unmigratable_flags = 0,
},
@@ -280,7 +316,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid = { .eax = 0x80000021, .reg = R_EAX, },
+ .cpuid = {
+ .eax = 0x80000021,
+ .reg = R_EAX,
+ },
.tcg_features = 0,
.unmigratable_flags = 0,
},
@@ -298,7 +337,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 0xd,
- .needs_ecx = true, .ecx = 1,
+ .needs_ecx = true,
+ .ecx = 1,
.reg = R_EAX,
},
.tcg_features = TCG_XSAVE_FEATURES,
@@ -328,7 +368,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.eax = 0xD,
.needs_ecx = true,
.ecx = 1,
- .reg = R_EDX
+ .reg = R_EDX,
},
},
[FEAT_6_EAX] = {
@@ -343,14 +383,18 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid = { .eax = 6, .reg = R_EAX, },
+ .cpuid = {
+ .eax = 6,
+ .reg = R_EAX,
+ },
.tcg_features = TCG_6_EAX_FEATURES,
},
[FEAT_XSAVE_XCR0_LO] = {
.type = CPUID_FEATURE_WORD,
.cpuid = {
.eax = 0xD,
- .needs_ecx = true, .ecx = 0,
+ .needs_ecx = true,
+ .ecx = 0,
.reg = R_EAX,
},
.tcg_features = ~0U,
@@ -363,7 +407,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = CPUID_FEATURE_WORD,
.cpuid = {
.eax = 0xD,
- .needs_ecx = true, .ecx = 0,
+ .needs_ecx = true,
+ .ecx = 0,
.reg = R_EDX,
},
.tcg_features = ~0U,
@@ -417,7 +462,6 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.index = MSR_IA32_PERF_CAPABILITIES,
},
},
-
[FEAT_VMX_PROCBASED_CTLS] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
@@ -432,9 +476,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.msr = {
.index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
- }
+ },
},
-
[FEAT_VMX_SECONDARY_CTLS] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
@@ -449,9 +492,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.msr = {
.index = MSR_IA32_VMX_PROCBASED_CTLS2,
- }
+ },
},
-
[FEAT_VMX_PINBASED_CTLS] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
@@ -466,9 +508,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.msr = {
.index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
- }
+ },
},
-
[FEAT_VMX_EXIT_CTLS] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
@@ -484,9 +525,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.msr = {
.index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
- }
+ },
},
-
[FEAT_VMX_ENTRY_CTLS] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
@@ -501,9 +541,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.msr = {
.index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
- }
+ },
},
-
[FEAT_VMX_MISC] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
@@ -518,9 +557,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.msr = {
.index = MSR_IA32_VMX_MISC,
- }
+ },
},
-
[FEAT_VMX_EPT_VPID_CAPS] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
@@ -544,9 +582,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.msr = {
.index = MSR_IA32_VMX_EPT_VPID_CAP,
- }
+ },
},
-
[FEAT_VMX_BASIC] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
@@ -559,7 +596,6 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
},
-
[FEAT_VMX_VMFUNC] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
@@ -567,9 +603,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.msr = {
.index = MSR_IA32_VMX_VMFUNC,
- }
+ },
},
-
[FEAT_14_0_ECX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
@@ -584,12 +619,12 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 0x14,
- .needs_ecx = true, .ecx = 0,
+ .needs_ecx = true,
+ .ecx = 0,
.reg = R_ECX,
},
.tcg_features = TCG_14_0_ECX_FEATURES,
- },
-
+ },
[FEAT_SGX_12_0_EAX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
@@ -604,16 +639,16 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 0x12,
- .needs_ecx = true, .ecx = 0,
+ .needs_ecx = true,
+ .ecx = 0,
.reg = R_EAX,
},
.tcg_features = TCG_SGX_12_0_EAX_FEATURES,
},
-
[FEAT_SGX_12_0_EBX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
- "sgx-exinfo" , NULL, NULL, NULL,
+ "sgx-exinfo", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@@ -624,12 +659,12 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 0x12,
- .needs_ecx = true, .ecx = 0,
+ .needs_ecx = true,
+ .ecx = 0,
.reg = R_EBX,
},
.tcg_features = TCG_SGX_12_0_EBX_FEATURES,
},
-
[FEAT_SGX_12_1_EAX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
@@ -644,7 +679,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.cpuid = {
.eax = 0x12,
- .needs_ecx = true, .ecx = 1,
+ .needs_ecx = true,
+ .ecx = 1,
.reg = R_EAX,
},
.tcg_features = TCG_SGX_12_1_EAX_FEATURES,
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 5/5] target/i386: Generate feature_word_info.c.inc
2024-02-06 13:47 [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
` (3 preceding siblings ...)
2024-02-06 13:47 ` [PATCH v3 4/5] target/i386: Fix feature_word_info.c.inc formatting Tim Wiederhake
@ 2024-02-06 13:47 ` Tim Wiederhake
2024-03-04 12:04 ` [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
2024-03-05 14:17 ` Daniel P. Berrangé
6 siblings, 0 replies; 10+ messages in thread
From: Tim Wiederhake @ 2024-02-06 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Philippe Mathieu-Daudé, Paolo Bonzini,
Daniel P . Berrangé, Michael S . Tsirkin, Tim Wiederhake
Signed-off-by: Tim Wiederhake <twiederh@redhat.com>
---
target/i386/feature_word_info.c.inc | 30 ++++++++++--
target/i386/feature_word_info.py | 71 +++++++++++++++++++++++++++++
target/i386/feature_word_info.yaml | 2 +
3 files changed, 99 insertions(+), 4 deletions(-)
create mode 100755 target/i386/feature_word_info.py
diff --git a/target/i386/feature_word_info.c.inc b/target/i386/feature_word_info.c.inc
index 4beae01918..b4bece08fe 100644
--- a/target/i386/feature_word_info.c.inc
+++ b/target/i386/feature_word_info.c.inc
@@ -1,3 +1,5 @@
+/* This file is generated by feature_word_info.py. */
+
FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_1_EDX] = {
.type = CPUID_FEATURE_WORD,
@@ -587,9 +589,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_VMX_BASIC] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
- [54] = "vmx-ins-outs",
- [55] = "vmx-true-ctls",
- [56] = "vmx-any-errcode",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, "vmx-ins-outs", "vmx-true-ctls",
+ "vmx-any-errcode", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
},
.msr = {
.index = MSR_IA32_VMX_BASIC,
@@ -599,7 +614,14 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_VMX_VMFUNC] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
- [0] = "vmx-eptp-switching",
+ "vmx-eptp-switching", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
},
.msr = {
.index = MSR_IA32_VMX_VMFUNC,
diff --git a/target/i386/feature_word_info.py b/target/i386/feature_word_info.py
new file mode 100755
index 0000000000..c9aa00900c
--- /dev/null
+++ b/target/i386/feature_word_info.py
@@ -0,0 +1,71 @@
+#!/bin/env python3
+
+import os
+import yaml
+
+
+def write_feature_word(f, data):
+ f.write(" [{}] = {{\n".format(data["index"]))
+ f.write(" .type = {},\n".format(data["type"]))
+
+ if "feat_names" in data:
+ keys = data.get("feat_names").keys()
+ if not keys or max(keys) < 32:
+ highest = 32
+ else:
+ highest = 64
+
+ f.write(" .feat_names = {\n")
+ for i in range(0, highest, 4):
+ names = [data.get("feat_names").get(j) for j in range(i, i + 4)]
+ names = ["NULL" if not name else f"\"{name}\"" for name in names]
+ display = ", ".join(names)
+ if len(display) < 90:
+ f.write(" {},\n".format(display))
+ else:
+ f.write(" {}, {},\n".format(names[0], names[1]))
+ f.write(" {}, {},\n".format(names[2], names[3]))
+ f.write(" },\n")
+ if "cpuid" in data:
+ cpuid = data["cpuid"]
+ f.write(" .cpuid = {\n")
+ f.write(" .eax = {},\n".format(cpuid["eax"]))
+ if "ecx" in cpuid:
+ f.write(" .needs_ecx = true,\n")
+ f.write(" .ecx = {},\n".format(cpuid["ecx"]))
+ f.write(" .reg = {},\n".format(cpuid["reg"]))
+ f.write(" },\n")
+ if "msr" in data:
+ f.write(" .msr = {\n")
+ f.write(" .index = {},\n".format(data["msr"]))
+ f.write(" },\n")
+ if "tcg_features" in data:
+ f.write(" .tcg_features = {},\n".format(data["tcg_features"]))
+ if "unmigratable_flags" in data:
+ f.write(" .unmigratable_flags = {},\n".format(
+ data["unmigratable_flags"]))
+ if "migratable_flags" in data:
+ f.write(" .migratable_flags = {},\n".format(
+ data["migratable_flags"]))
+ if "no_autoenable_flags" in data:
+ f.write(" .no_autoenable_flags = {},\n".format(
+ data["no_autoenable_flags"]))
+ f.write(" },\n")
+
+
+def main():
+ dirname = os.path.dirname(__file__)
+
+ with open(os.path.join(dirname, "feature_word_info.yaml"), "tr") as f:
+ feature_words = yaml.safe_load(f)
+
+ with open(os.path.join(dirname, "feature_word_info.c.inc"), "tw") as f:
+ f.write("/* This file is generated by feature_word_info.py. */\n\n")
+ f.write("FeatureWordInfo feature_word_info[FEATURE_WORDS] = {\n")
+ for feature_word in feature_words:
+ write_feature_word(f, feature_word)
+ f.write("};\n")
+
+
+if __name__ == "__main__":
+ main()
diff --git a/target/i386/feature_word_info.yaml b/target/i386/feature_word_info.yaml
index 7a8ca3f051..0e9dbcb613 100644
--- a/target/i386/feature_word_info.yaml
+++ b/target/i386/feature_word_info.yaml
@@ -1,3 +1,5 @@
+# Run feature_word_info.py if you make changes to this file!
+
- index: FEAT_1_EDX
cpuid:
eax: '1'
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 0/5] Generate x86 cpu features
2024-02-06 13:47 [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
` (4 preceding siblings ...)
2024-02-06 13:47 ` [PATCH v3 5/5] target/i386: Generate feature_word_info.c.inc Tim Wiederhake
@ 2024-03-04 12:04 ` Tim Wiederhake
2024-03-05 14:17 ` Daniel P. Berrangé
6 siblings, 0 replies; 10+ messages in thread
From: Tim Wiederhake @ 2024-03-04 12:04 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Philippe Mathieu-Daudé, Paolo Bonzini,
Daniel P . Berrangé, Michael S . Tsirkin
ping
On Tue, 2024-02-06 at 14:47 +0100, Tim Wiederhake wrote:
> Synchronizing the list of cpu features and models with qemu is a
> recurring
> task in libvirt. For x86, this is done by reading qom-list-properties
> for
> max-x86_64-cpu and manually filtering out everthing that does not
> look like
> a feature name, as well as parsing target/i386/cpu.c for cpu models.
>
> This is a flawed, tedious and error-prone procedure. Ideally, qemu
> and libvirt would query a common source for cpu feature and model
> related information. Meanwhile, converting this information into an
> easier
> to parse format would help libvirt a lot.
>
> This patch series converts the cpu feature information present in
> target/i386/cpu.c (`feature_word_info`) into a yaml file and adds a
> script to generate the c code from this data.
>
> v1:
> https://lists.nongnu.org/archive/html/qemu-devel/2023-08/msg02005.html
> v2:
> https://lists.nongnu.org/archive/html/qemu-devel/2023-09/msg01773.html
>
> Changes since v2:
> * Rebased on top of current master
> * Removed all "drive-by" changes to feature names ("vmx-ept-uc",
> "vmx-ept-wb",
> "kvmclock", "vmx-invept-single-context", and
> "vmx-invept-single-context-noglobals") as these needed further
> discussion.
> * Changes to the generator script reduce the changes in formatting to
> the
> current feature_word_info even further to address the concern about
> code
> legibility. See Patch 5, "target/i386: Generate
> feature_word_info.c.inc" for
> all non-whitespace changes.
>
> Tim Wiederhake (5):
> target/i386: Split out feature_word_info
> target/i386: Translate feature_word_info to yaml
> target/i386: Remove comments from feature_word_info.c.inc
> target/i386: Fix feature_word_info.c.inc formatting
> target/i386: Generate feature_word_info.c.inc
>
> target/i386/cpu.c | 679 +-------------------------
> target/i386/feature_word_info.c.inc | 710
> ++++++++++++++++++++++++++++
> target/i386/feature_word_info.py | 71 +++
> target/i386/feature_word_info.yaml | 701
> +++++++++++++++++++++++++++
> 4 files changed, 1483 insertions(+), 678 deletions(-)
> create mode 100644 target/i386/feature_word_info.c.inc
> create mode 100755 target/i386/feature_word_info.py
> create mode 100644 target/i386/feature_word_info.yaml
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 0/5] Generate x86 cpu features
2024-02-06 13:47 [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
` (5 preceding siblings ...)
2024-03-04 12:04 ` [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
@ 2024-03-05 14:17 ` Daniel P. Berrangé
2024-03-11 11:32 ` Tim Wiederhake
6 siblings, 1 reply; 10+ messages in thread
From: Daniel P. Berrangé @ 2024-03-05 14:17 UTC (permalink / raw)
To: Tim Wiederhake
Cc: qemu-devel, Igor Mammedov, Philippe Mathieu-Daudé,
Paolo Bonzini, Michael S . Tsirkin
On Tue, Feb 06, 2024 at 02:47:34PM +0100, Tim Wiederhake wrote:
> Synchronizing the list of cpu features and models with qemu is a recurring
> task in libvirt. For x86, this is done by reading qom-list-properties for
> max-x86_64-cpu and manually filtering out everthing that does not look like
> a feature name, as well as parsing target/i386/cpu.c for cpu models.
>
> This is a flawed, tedious and error-prone procedure. Ideally, qemu
> and libvirt would query a common source for cpu feature and model
> related information. Meanwhile, converting this information into an easier
> to parse format would help libvirt a lot.
>
> This patch series converts the cpu feature information present in
> target/i386/cpu.c (`feature_word_info`) into a yaml file and adds a
> script to generate the c code from this data.
Looking at this fresh, I'm left wondering why I didn't suggested
using 'QMP' to expose this information when reviewing the earlier
versions. I see Igor did indeed suggest this:
https://lists.nongnu.org/archive/html/qemu-devel/2023-09/msg03905.html
Your commentry that "qom-list-properties" doesn't distinguish
between CPU features and other random QOM properties is bang
on the money.
I think what this highlights, is that 'qom-list-properties'
is a very poor design/fit for the problem that management apps
need to solve in this regard.
Libvirt should not need to manually exclude non-feature properties
like 'check' 'enforce' 'migratable' etc.
QEMU already has this knowledge, as IIUC, 'query-cpu-model-expansion'
can distinguish this:
query-cpu-model-expansion type=static model={'name':'Nehalem'}
{
"return": {
"model": {
"name": "base",
"props": {
"3dnow": false,
...snip...
"xtpr": false
}
}
}
}
We still have the problem that we're not exposing the CPUID/MSR
leafs/register bits. So query-cpu-model-expansion isn't a fit
for the problem.
Rather than try to design something super general purpose, I'd
suggest we take a short cut and design something entirley x86
specific, and simply mark the QMP command as "unstable"
eg a 'x-query-x86-cpu-model-features', and then basically
report all the information libvirt needs there.
This is functionally equivalent to what you expose in the YAML
file, while still using QEMU's formal 'QMP' API mechanism, so
we avoid inventing a new API concept via YAML.
I think this would avoid need to have a code generator refactor
the CPU definitions too. We just need to expose the values of
the existing CPUID_xxx constants against each register.
With regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 0/5] Generate x86 cpu features
2024-03-05 14:17 ` Daniel P. Berrangé
@ 2024-03-11 11:32 ` Tim Wiederhake
2024-03-11 11:58 ` Daniel P. Berrangé
0 siblings, 1 reply; 10+ messages in thread
From: Tim Wiederhake @ 2024-03-11 11:32 UTC (permalink / raw)
To: Daniel P. Berrangé
Cc: qemu-devel, Igor Mammedov, Philippe Mathieu-Daudé,
Paolo Bonzini, Michael S . Tsirkin
On Tue, 2024-03-05 at 14:17 +0000, Daniel P. Berrangé wrote:
> > On Tue, Feb 06, 2024 at 02:47:34PM +0100, Tim Wiederhake wrote:
> > > > Synchronizing the list of cpu features and models with qemu is
> > > > a
> > > > recurring
> > > > task in libvirt. For x86, this is done by reading
> > > > qom-list-properties for
> > > > max-x86_64-cpu and manually filtering out everthing that does
> > > > not
> > > > look like
> > > > a feature name, as well as parsing target/i386/cpu.c for cpu
> > > > models.
> > > >
> > > > This is a flawed, tedious and error-prone procedure. Ideally,
> > > > qemu
> > > > and libvirt would query a common source for cpu feature and
> > > > model
> > > > related information. Meanwhile, converting this information
> > > > into an
> > > > easier
> > > > to parse format would help libvirt a lot.
> > > >
> > > > This patch series converts the cpu feature information present
> > > > in
> > > > target/i386/cpu.c (`feature_word_info`) into a yaml file and
> > > > adds a
> > > > script to generate the c code from this data.
> >
> > Looking at this fresh, I'm left wondering why I didn't suggested
> > using 'QMP' to expose this information when reviewing the earlier
> > versions. I see Igor did indeed suggest this:
> >
> >
> > https://lists.nongnu.org/archive/html/qemu-devel/2023-09/msg03905.html
> >
> > Your commentry that "qom-list-properties" doesn't distinguish
> > between CPU features and other random QOM properties is bang
> > on the money.
> >
> > I think what this highlights, is that 'qom-list-properties'
> > is a very poor design/fit for the problem that management apps
> > need to solve in this regard.
> >
> > Libvirt should not need to manually exclude non-feature properties
> > like 'check' 'enforce' 'migratable' etc.
> >
> > QEMU already has this knowledge, as IIUC, 'query-cpu-model-
> > expansion'
> > can distinguish this:
> >
> > query-cpu-model-expansion type=static model={'name':'Nehalem'}
> > {
> > "return": {
> > "model": {
> > "name": "base",
> > "props": {
> > "3dnow": false,
> > ...snip...
> > "xtpr": false
> > }
> > }
> > }
> > }
> >
> > We still have the problem that we're not exposing the CPUID/MSR
> > leafs/register bits. So query-cpu-model-expansion isn't a fit
> > for the problem.
> >
> > Rather than try to design something super general purpose, I'd
> > suggest we take a short cut and design something entirley x86
> > specific, and simply mark the QMP command as "unstable"
> > eg a 'x-query-x86-cpu-model-features', and then basically
> > report all the information libvirt needs there.
> >
> > This is functionally equivalent to what you expose in the YAML
> > file, while still using QEMU's formal 'QMP' API mechanism, so
> > we avoid inventing a new API concept via YAML.
> >
> > I think this would avoid need to have a code generator refactor
> > the CPU definitions too. We just need to expose the values of
> > the existing CPUID_xxx constants against each register.
> >
> >
> >
> > With regards,
> > Daniel
Thank you for your feedback.
I do not see the patches and your proposed x-query-x86-cpu-model-
features QMP command being mutually exclusive.
In fact, I'd advocate for merging this patches still, as they provide a
solution (albeit not through QMP) already whereas the QMP command would
still need to be written. Additionally, there are more benefits to the
generate-code approach, as the code generator can be extended to also
generate the feature bits "#define CPUID_* (1U << ...)" in cpu.h,
removing one more source of errors. And with the generated
`feature_word_info` structure being virtually identical to the current
version, I see no downsides: If the generator does become obsolete in
the future, simply remove the python script and the yaml file, and all
that is left is the original feature_word_info code, but better
formatted.
Regards,
Tim
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 0/5] Generate x86 cpu features
2024-03-11 11:32 ` Tim Wiederhake
@ 2024-03-11 11:58 ` Daniel P. Berrangé
0 siblings, 0 replies; 10+ messages in thread
From: Daniel P. Berrangé @ 2024-03-11 11:58 UTC (permalink / raw)
To: Tim Wiederhake
Cc: qemu-devel, Igor Mammedov, Philippe Mathieu-Daudé,
Paolo Bonzini, Michael S . Tsirkin
On Mon, Mar 11, 2024 at 12:32:03PM +0100, Tim Wiederhake wrote:
> On Tue, 2024-03-05 at 14:17 +0000, Daniel P. Berrangé wrote:
> > > Looking at this fresh, I'm left wondering why I didn't suggested
> > > using 'QMP' to expose this information when reviewing the earlier
> > > versions. I see Igor did indeed suggest this:
> > >
> > >
> > > https://lists.nongnu.org/archive/html/qemu-devel/2023-09/msg03905.html
> > >
> > > Your commentry that "qom-list-properties" doesn't distinguish
> > > between CPU features and other random QOM properties is bang
> > > on the money.
> > >
> > > I think what this highlights, is that 'qom-list-properties'
> > > is a very poor design/fit for the problem that management apps
> > > need to solve in this regard.
> > >
> > > Libvirt should not need to manually exclude non-feature properties
> > > like 'check' 'enforce' 'migratable' etc.
> > >
> > > QEMU already has this knowledge, as IIUC, 'query-cpu-model-
> > > expansion'
> > > can distinguish this:
> > >
> > > query-cpu-model-expansion type=static model={'name':'Nehalem'}
> > > {
> > > "return": {
> > > "model": {
> > > "name": "base",
> > > "props": {
> > > "3dnow": false,
> > > ...snip...
> > > "xtpr": false
> > > }
> > > }
> > > }
> > > }
> > >
> > > We still have the problem that we're not exposing the CPUID/MSR
> > > leafs/register bits. So query-cpu-model-expansion isn't a fit
> > > for the problem.
> > >
> > > Rather than try to design something super general purpose, I'd
> > > suggest we take a short cut and design something entirley x86
> > > specific, and simply mark the QMP command as "unstable"
> > > eg a 'x-query-x86-cpu-model-features', and then basically
> > > report all the information libvirt needs there.
> > >
> > > This is functionally equivalent to what you expose in the YAML
> > > file, while still using QEMU's formal 'QMP' API mechanism, so
> > > we avoid inventing a new API concept via YAML.
> > >
> > > I think this would avoid need to have a code generator refactor
> > > the CPU definitions too. We just need to expose the values of
> > > the existing CPUID_xxx constants against each register.
>
> I do not see the patches and your proposed x-query-x86-cpu-model-
> features QMP command being mutually exclusive.
>
> In fact, I'd advocate for merging this patches still, as they provide a
> solution (albeit not through QMP) already whereas the QMP command would
> still need to be written.
I would not class this as an advantage for QEMU in merging this
series. It is defining what amounts to a new externally consumable
interface for QEMU, which is intended to be used by libvirt. Even
if it not consumed at runtime, it is still implying API guarantees.
QEMU really does not want to be adding new interfaces, as there is
a strong desire to reduce all external interaction with QEMU to
exclusively be QMP based.
> Additionally, there are more benefits to the
> generate-code approach, as the code generator can be extended to also
> generate the feature bits "#define CPUID_* (1U << ...)" in cpu.h,
> removing one more source of errors. And with the generated
> `feature_word_info` structure being virtually identical to the current
> version, I see no downsides: If the generator does become obsolete in
> the future, simply remove the python script and the yaml file, and all
> that is left is the original feature_word_info code, but better
> formatted.
If we external usage, then we're left with a pretty weak justification
for introducing a new custom code generator here IMHO.
In terms of the CPUID_ constants, I think what would make more sense
from QEMU's POV is to define them all as a QAPI enum.
eg
{ 'enum': 'CPUID',
'data': [
'fpu', 'vme', 'de', 'pse', 'tsc',
.....
] }
which will result in QAPI generating constants
CPUID_VME
CPUID_FPU
CPUID_DE
...etc
along with a constant <-> string conversion table.
The feature words could use the constants directly instead of their
string form
FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_1_EDX] = {
.type = CPUID_FEATURE_WORD,
.features = {
[0] = CPUID_FPU,
[1] = CPUID_VME,
[2] = CPUID_DE,
...etc...
},
.cpuid = {.eax = 1, .reg = R_EDX, },
.tcg_features = TCG_FEATURES,
.no_autoenable_flags = CPUID_HT,
},
which I think encodes the information just as effectively as the yaml
file does.
With regards,
Daniel
--
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-03-11 11:58 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-02-06 13:47 [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 1/5] target/i386: Split out feature_word_info Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 2/5] target/i386: Translate feature_word_info to yaml Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 3/5] target/i386: Remove comments from feature_word_info.c.inc Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 4/5] target/i386: Fix feature_word_info.c.inc formatting Tim Wiederhake
2024-02-06 13:47 ` [PATCH v3 5/5] target/i386: Generate feature_word_info.c.inc Tim Wiederhake
2024-03-04 12:04 ` [PATCH v3 0/5] Generate x86 cpu features Tim Wiederhake
2024-03-05 14:17 ` Daniel P. Berrangé
2024-03-11 11:32 ` Tim Wiederhake
2024-03-11 11:58 ` Daniel P. Berrangé
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