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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>,
	Gustavo Romero <gustavo.romero@linaro.org>,
	qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH v7 4/6] target/arm: Add FEAT_TCR2
Date: Mon, 14 Jul 2025 08:46:34 -0700	[thread overview]
Message-ID: <eabfd320-5efd-4a0a-807e-10aca82ca27b@linaro.org> (raw)
In-Reply-To: <f18a652e-b64c-4a33-bd60-63dfa93ffdbd@linaro.org>

On 7/14/25 5:58 AM, Richard Henderson wrote:
> On 7/14/25 00:21, Pierrick Bouvier wrote:
>> On 7/13/25 2:59 PM, Richard Henderson wrote:
>>> On 7/11/25 08:08, Gustavo Romero wrote:
>>>> Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers.
>>>> These registers are extensions of the TCR_ELx registers and provide
>>>> top-level control of the EL10 and EL20 translation regimes.
>>>>
>>>> Since the bits in these registers depend on other CPU features, and only
>>>> FEAT_MEC is supported at the moment, the FEAT_TCR2 only implements the
>>>> AMEC bits for now.
>>>>
>>>> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
>>> This causes a regression in tests/functional/test_aarch64_device_passthrough.py, by
>>> continually trapping on an access to TCR2_EL1 while the HCRX_EL2 enable bit is not set.
>>>
>>> Unlike the similar SCTRL2 failure, it's not 100% clear to me how the guest and nested
>>> guest kernels are related.  But it is clear that the outer kernel does not does not
>>> support TCR2_EL1 (and also doesn't manipulate ID_AA64MMFR3_EL1 to hide FEAT_TCR2), but the
>>> nested guest kernel does support TCR2_EL1.
>>>
>>
>> The same kernel is used for host and guest.
>> Maybe it's related to kvm support?
> 
> Oops, no, the patch fails to enable HCRX_TCR2EN in hcrx_write or SCR_TCR2EN in scr_write.
> The same is true for the previous patch with HCRX_SCTLR2EN and SCR_SCTLR2EN.
> 

Thanks for the investigation. Indeed, building TF-A with 
ENABLE_FEAT_TCR2 and ENABLE_FEAT_SCTRL2 didn't change anything.

It's possible that it's still needed to update test images though, so 
I'll try when Gustavo will post v8.

Thanks,
Pierrick

> 
> r~



  parent reply	other threads:[~2025-07-14 16:48 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-11 14:08 [PATCH-for-10.1 v7 0/6] target/arm: Add FEAT_MEC to max cpu Gustavo Romero
2025-07-11 14:08 ` [PATCH v7 1/6] target/arm: Add the MECEn SCR_EL3 bit Gustavo Romero
2025-07-11 14:08 ` [PATCH v7 2/6] target/arm: Add FEAT_MEC registers Gustavo Romero
2025-07-11 14:08 ` [PATCH v7 3/6] target/arm: Add FEAT_SCTLR2 Gustavo Romero
     [not found]   ` <09497926-db8a-4475-b361-7e8338597326@linaro.org>
2025-07-13 16:27     ` Richard Henderson
2025-07-14  5:43       ` Pierrick Bouvier
2025-07-11 14:08 ` [PATCH v7 4/6] target/arm: Add FEAT_TCR2 Gustavo Romero
2025-07-13 21:59   ` Richard Henderson
2025-07-14  6:21     ` Pierrick Bouvier
2025-07-14 12:58       ` Richard Henderson
2025-07-14 13:36         ` Gustavo Romero
2025-07-14 15:46         ` Pierrick Bouvier [this message]
2025-07-11 14:08 ` [PATCH v7 5/6] target/arm: Implement FEAT_MEC cache instructions Gustavo Romero
2025-07-11 14:08 ` [PATCH v7 6/6] target/arm: Advertise FEAT_MEC in cpu max Gustavo Romero

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