From: Joel Upham <jupham125@gmail.com>
To: qemu-devel@nongnu.org
Cc: Joel Upham <jupham125@gmail.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Anthony Perard <anthony.perard@citrix.com>,
Paul Durrant <paul@xen.org>,
xen-devel@lists.xenproject.org (open list:X86 Xen CPUs)
Subject: [PATCH v1 13/23] xen/pt: add Vendor-specific PCIe Extended Capability descriptor and sizing
Date: Tue, 20 Jun 2023 13:24:47 -0400 [thread overview]
Message-ID: <ead3c0639b91d0d0c12f91f3f1b4024547a9a0b4.1687278381.git.jupham125@gmail.com> (raw)
In-Reply-To: <cover.1687278381.git.jupham125@gmail.com>
The patch provides Vendor-specific PCIe Extended Capability description
structure and corresponding sizing function. In this particular case the
size of the Vendor capability is available in the VSEC Length field.
Signed-off-by: Alexey Gerasimenko <x1917x@xxxxxxxxx>
Signed-off-by: Joel Upham <jupham125@gmail.com>
---
hw/xen/xen_pt_config_init.c | 71 ++++++++++++++++++++++++++++++++++++-
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
index ed36edbc4a..20b5561d25 100644
--- a/hw/xen/xen_pt_config_init.c
+++ b/hw/xen/xen_pt_config_init.c
@@ -124,6 +124,17 @@ static uint32_t get_throughable_mask(const XenPCIPassthroughState *s,
return throughable_mask & valid_mask;
}
+static void log_pcie_extended_cap(XenPCIPassthroughState *s,
+ const char *cap_name,
+ uint32_t base_offset, uint32_t size)
+{
+ if (size) {
+ XEN_PT_LOG(&s->dev, "Found PCIe Extended Capability: %s at 0x%04x, "
+ "size 0x%x bytes\n", cap_name,
+ (uint16_t) base_offset, size);
+ }
+}
+
/****************
* general register functions
*/
@@ -1622,6 +1633,42 @@ static XenPTRegInfo xen_pt_emu_reg_igd_opregion[] = {
},
};
+/* Vendor-specific Ext Capability Structure reg static information table */
+static XenPTRegInfo xen_pt_ext_cap_emu_reg_vendor[] = {
+ {
+ .offset = XEN_PCIE_CAP_ID,
+ .size = 2,
+ .init_val = 0x0000,
+ .ro_mask = 0xFFFF,
+ .emu_mask = 0xFFFF,
+ .init = xen_pt_ext_cap_capid_reg_init,
+ .u.w.read = xen_pt_word_reg_read,
+ .u.w.write = xen_pt_word_reg_write,
+ },
+ {
+ .offset = XEN_PCIE_CAP_LIST_NEXT,
+ .size = 2,
+ .init_val = 0x0000,
+ .ro_mask = 0xFFFF,
+ .emu_mask = 0xFFFF,
+ .init = xen_pt_ext_cap_ptr_reg_init,
+ .u.w.read = xen_pt_word_reg_read,
+ .u.w.write = xen_pt_word_reg_write,
+ },
+ {
+ .offset = PCI_VNDR_HEADER,
+ .size = 4,
+ .init_val = 0x00000000,
+ .ro_mask = 0xFFFFFFFF,
+ .emu_mask = 0x00000000,
+ .init = xen_pt_common_reg_init,
+ .u.dw.read = xen_pt_long_reg_read,
+ .u.dw.write = xen_pt_long_reg_write,
+ },
+ {
+ .size = 0,
+ },
+};
/****************************
* Capabilities
*/
@@ -1647,9 +1694,23 @@ static int xen_pt_vendor_size_init(XenPCIPassthroughState *s,
return ret;
}
+static int xen_pt_ext_cap_vendor_size_init(XenPCIPassthroughState *s,
+ const XenPTRegGroupInfo *grp_reg,
+ uint32_t base_offset,
+ uint32_t *size)
{
- return xen_host_pci_get_byte(&s->real_device, base_offset + 0x02, size);
+ uint32_t vsec_hdr = 0;
+ int ret = xen_host_pci_get_long(&s->real_device,
+ base_offset + PCI_VNDR_HEADER,
+ &vsec_hdr);
+
+ *size = PCI_VNDR_HEADER_LEN(vsec_hdr);
+
+ log_pcie_extended_cap(s, "Vendor-specific", base_offset, *size);
+
+ return ret;
}
+
/* get PCI Express Capability Structure register group size */
static int xen_pt_pcie_size_init(XenPCIPassthroughState *s,
const XenPTRegGroupInfo *grp_reg,
@@ -1876,6 +1937,14 @@ static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
.size_init = xen_pt_reg_grp_size_init,
.emu_regs = xen_pt_emu_reg_igd_opregion,
},
+ /* Vendor-specific Extended Capability reg group */
+ {
+ .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_VNDR),
+ .grp_type = XEN_PT_GRP_TYPE_EMU,
+ .grp_size = 0xFF,
+ .size_init = xen_pt_ext_cap_vendor_size_init,
+ .emu_regs = xen_pt_ext_cap_emu_reg_vendor,
+ },
{
.grp_size = 0,
},
--
2.34.1
next prev parent reply other threads:[~2023-06-20 19:47 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-20 17:24 [PATCH v1 00/23] Q35 support for Xen Joel Upham
2023-06-20 17:24 ` [PATCH v1 01/23] pc/xen: Xen Q35 support: provide IRQ handling for PCI devices Joel Upham
2023-06-21 7:17 ` Daniel P. Berrangé
2023-06-21 16:49 ` Joel Upham
2023-08-29 10:18 ` David Woodhouse
2023-08-29 14:20 ` David Woodhouse
2023-06-20 17:24 ` [PATCH v1 02/23] pc/q35: Apply PCI bus BSEL property for Xen PCI device hotplug Joel Upham
2023-06-21 11:27 ` Igor Mammedov
2023-06-21 17:24 ` Joel Upham
2023-06-22 7:35 ` Igor Mammedov
2023-06-22 16:51 ` Julia Suvorova
2023-06-20 17:24 ` [PATCH v1 03/23] q35/acpi/xen: Provide ACPI PCI hotplug interface for Xen on Q35 Joel Upham
2023-06-21 11:28 ` Igor Mammedov
2023-06-21 17:27 ` Joel Upham
2023-06-20 17:24 ` [PATCH v1 04/23] q35/xen: Add Xen platform device support for Q35 Joel Upham
2023-06-20 17:24 ` [PATCH v1 05/23] q35: Fix incorrect values for PCIEXBAR masks Joel Upham
2023-06-20 17:24 ` [PATCH v1 06/23] xen/pt: XenHostPCIDevice: provide functions for PCI Capabilities and PCIe Extended Capabilities enumeration Joel Upham
2023-06-20 17:24 ` [PATCH v1 07/23] xen/pt: avoid reading PCIe device type and cap version multiple times Joel Upham
2023-06-20 17:24 ` [PATCH v1 08/23] xen/pt: determine the legacy/PCIe mode for a passed through device Joel Upham
2023-06-20 17:24 ` [PATCH v1 09/23] xen/pt: Xen PCIe passthrough support for Q35: bypass PCIe topology check Joel Upham
2023-06-20 17:24 ` [PATCH v1 10/23] xen/pt: add support for PCIe Extended Capabilities and larger config space Joel Upham
2023-06-20 17:24 ` [PATCH v1 11/23] xen/pt: handle PCIe Extended Capabilities Next register Joel Upham
2023-06-20 17:24 ` [PATCH v1 12/23] xen/pt: allow to hide PCIe Extended Capabilities Joel Upham
2023-06-20 17:24 ` Joel Upham [this message]
2023-06-20 17:24 ` [PATCH v1 14/23] xen/pt: add fixed-size PCIe Extended Capabilities descriptors Joel Upham
2023-06-20 17:24 ` [PATCH v1 15/23] xen/pt: add AER PCIe Extended Capability descriptor and sizing Joel Upham
2023-06-20 17:24 ` [PATCH v1 16/23] xen/pt: add descriptors and size calculation for RCLD/ACS/PMUX/DPA/MCAST/TPH/DPC PCIe Extended Capabilities Joel Upham
2023-06-20 17:24 ` [PATCH v1 17/23] xen/pt: add Resizable BAR PCIe Extended Capability descriptor and sizing Joel Upham
2023-06-20 17:24 ` [PATCH v1 18/23] xen/pt: add VC/VC9/MFVC PCIe Extended Capabilities descriptors " Joel Upham
2023-06-20 17:24 ` [PATCH v1 19/23] xen/pt: Fake capability id Joel Upham
2023-06-20 17:24 ` [PATCH v1 20/23] xen platform: unplug ahci object Joel Upham
2023-06-22 5:40 ` Bernhard Beschow
2023-10-19 12:37 ` David Woodhouse
2023-06-20 17:24 ` [PATCH v1 21/23] pc/q35: setup q35 for xen Joel Upham
2023-06-20 17:24 ` [PATCH v1 22/23] qdev-monitor/pt: bypass root device check Joel Upham
2023-06-20 17:24 ` [PATCH v1 23/23] s3 support: enabling s3 with q35 Joel Upham
2023-06-21 11:34 ` Igor Mammedov
2023-06-21 17:40 ` Joel Upham
2023-06-22 17:10 ` [PATCH v1 00/23] Q35 support for Xen Bernhard Beschow
2023-07-05 16:50 ` Joel Upham
2023-07-05 22:24 ` Bernhard Beschow
2023-08-22 14:18 ` Anthony PERARD
2023-08-22 17:15 ` Joel Upham
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ead3c0639b91d0d0c12f91f3f1b4024547a9a0b4.1687278381.git.jupham125@gmail.com \
--to=jupham125@gmail.com \
--cc=anthony.perard@citrix.com \
--cc=paul@xen.org \
--cc=qemu-devel@nongnu.org \
--cc=sstabellini@kernel.org \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).