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[93.34.153.63]) by smtp.gmail.com with ESMTPSA id c65sm1407295wma.44.2019.06.28.02.35.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 28 Jun 2019 02:35:50 -0700 (PDT) To: Lucien Murray-Pitts References: <2136180936.260219.1561641583358.ref@mail.yahoo.com> <2136180936.260219.1561641583358@mail.yahoo.com> <1079763171.281101.1561641752988@mail.yahoo.com> <20190628002713.GA19257@localhost.localdomain> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: Date: Fri, 28 Jun 2019 11:35:48 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190628002713.GA19257@localhost.localdomain> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::431 Subject: Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucien Anti-Spam , qemu-devel@nongnu.org, Laurent Vivier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/28/19 2:27 AM, Lucien Murray-Pitts wrote: > The original way of handling it was causing single step to malfunction, I dont > rightly know why but the effect was that step would step twice and end up > inside the ISR function again OR just stepping past the RTE as if it didnt > exist. > > I have made a quick hack to implement it the way you suggest and confirm that > works better. > > HOWEVER, the "return" address is the instruction that causes the exception. > So it immediately does return to the ISR. > > This is a different issue, but I think interrelated to the original problem. Is this a synchronous exception, like a SIGSEGV, that the instruction is causing? I have made attempts at fixing asynchronous interrupts, like the clock, in the presence of single-stepping. I haven't tested that in a while and I hope it's still working... > Further single stepping INTO the failing instruction results in ending up > at the ISR +1 instruction For a synchronous exception, that sounds like a real bug. Probably within cpu_handle_exception, #else if (replay_exception()) { CPUClass *cc = CPU_GET_CLASS(cpu); qemu_mutex_lock_iothread(); cc->do_interrupt(cpu); qemu_mutex_unlock_iothread(); + /* Single-step into the exception handler. */ + if (cpu->singlestep_enabled) { + cpu_handle_debug_exception(cpu); + } cpu->exception_index = -1; } else if (!replay_has_interrupt()) { r~