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([2602:47:d490:6901:e72:57bd:c5e4:990c]) by smtp.gmail.com with ESMTPSA id g4-20020a1709026b4400b001bb24cb9a61sm4914175plt.265.2023.08.06.06.46.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 06 Aug 2023 06:46:01 -0700 (PDT) Message-ID: Date: Sun, 6 Aug 2023 06:45:58 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 6/7] tcg/ppc: Disable USE_REG_TB for Power v3.1 Content-Language: en-US To: Nicholas Piggin , qemu-devel@nongnu.org Cc: jniethe5@gmail.com, qemu-ppc@nongnu.org, bgray@linux.ibm.com References: <20230804213355.294443-1-richard.henderson@linaro.org> <20230804213355.294443-7-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -61 X-Spam_score: -6.2 X-Spam_bar: ------ X-Spam_report: (-6.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-4.139, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/6/23 04:58, Nicholas Piggin wrote: > Patch 7 is not reqired for this? No, USE_REG_TB has never been *required*. The fallback path through tcg_out_movi will generate the 5 insn sequence for a full 64-bit constant load. Mitigating that here is that patch 1 will emit PADDI for most of those constants. r~ > > Thanks, > Nick > > On Sat Aug 5, 2023 at 7:33 AM AEST, Richard Henderson wrote: >> With Power v3.1, we have pc-relative addressing and so >> do not require a register holding the current TB. >> >> Signed-off-by: Richard Henderson >> --- >> tcg/ppc/tcg-target.c.inc | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc >> index e8eced7cf3..5b243b2353 100644 >> --- a/tcg/ppc/tcg-target.c.inc >> +++ b/tcg/ppc/tcg-target.c.inc >> @@ -83,7 +83,7 @@ >> #define TCG_VEC_TMP2 TCG_REG_V1 >> >> #define TCG_REG_TB TCG_REG_R31 >> -#define USE_REG_TB (TCG_TARGET_REG_BITS == 64) >> +#define USE_REG_TB (TCG_TARGET_REG_BITS == 64 && !have_isa_3_10) >> >> /* Shorthand for size of a pointer. Avoid promotion to unsigned. */ >> #define SZP ((int)sizeof(void *)) >