From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-stable@nongnu.org
Subject: Re: [PATCH for-9.0] target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
Date: Mon, 25 Mar 2024 08:28:41 -1000 [thread overview]
Message-ID: <eb736a6e-59fe-4b3f-9338-fb94d13fce32@linaro.org> (raw)
In-Reply-To: <20240325133116.2075362-1-peter.maydell@linaro.org>
On 3/25/24 03:31, Peter Maydell wrote:
> The HSTR_EL2 register allows the hypervisor to trap AArch32 EL1 and
> EL0 accesses to cp15 registers. We incorrectly implemented this so
> they trap to EL1 when we detect the need for a HSTR trap at code
> generation time. (The check in access_check_cp_reg() which we do at
> runtime to catch traps from EL0 is correctly routing them to EL2.)
>
> Use the correct target EL when generating the code to take the trap.
>
> Cc:qemu-stable@nongnu.org
> Resolves:https://gitlab.com/qemu-project/qemu/-/issues/2226
> Fixes: 049edada5e93df ("target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1")
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> target/arm/tcg/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
prev parent reply other threads:[~2024-03-25 18:29 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-25 13:31 [PATCH for-9.0] target/arm: take HSTR traps of cp15 accesses to EL2, not EL1 Peter Maydell
2024-03-25 18:28 ` Richard Henderson [this message]
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