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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Fri, 29 Jun 2018 07:54:30 -0700
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Subject: Re: [Qemu-devel] [PATCH 6/6] target/arm: Set ISAR bits for -cpu max
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>

On 06/29/2018 01:42 AM, Peter Maydell wrote:
> On 29 June 2018 at 01:15, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> For the supported extensions, fill in the appropriate bits in
>> ID_ISAR5, ID_ISAR6, ID_AA64ISAR0, ID_AA64ISAR1.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
> 
> This makes sense, but I'd rather have a bit of time to think
> about how exactly we want to handle feature bits vs ID
> register values (the current codebase is not entirely
> coherent on the topic), so I'd rather not put this in
> for softfreeze unless there's a strong reason we should...

Fair.

I was wondering if we'd post-process the feature bits to initialize the id
registers, so that we don't have different places with the same knowledge.

The clearing of EL3 bits from id_pfr1 is an example of that already.


r~