From: LIU Zhiwei <liuzwnan@163.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: rajav@quicinc.com, qemu-arm@nongnu.org, apazos@quicinc.com
Subject: Re: [PATCH for-5.1 00/31] target/arm: SVE2, part 1
Date: Wed, 22 Apr 2020 10:51:05 +0800 [thread overview]
Message-ID: <eb7eea48-ecb8-f64d-83cd-66463a61d5a6@163.com> (raw)
In-Reply-To: <20200326230838.31112-1-richard.henderson@linaro.org>
Hi Richard,
I find BF16 is included in the ISA. Will you extend the softfpu in
this patch set?
Zhiwei
On 2020/3/27 7:08, Richard Henderson wrote:
> Posting this for early review. It's based on some other patch
> sets that I have posted recently that also touch SVE, listed
> below. But it might just be easier to clone the devel tree [2].
> While the branch itself will rebase frequently for development,
> I've also created a tag, post-sve2-20200326, for this posting.
>
> This is mostly untested, as the most recently released Foundation
> Model does not support SVE2. Some of the new instructions overlap
> with old fashioned NEON, and I can verify that those have not
> broken, and show that SVE2 will use the same code path. But the
> predicated insns and bottom/top interleaved insns are not yet
> RISU testable, as I have nothing to compare against.
>
> The patches are in general arranged so that one complete group
> of insns are added at once. The groups within the manual [1]
> have so far been small-ish.
>
>
> r~
>
> ---
>
> [1] ISA manual: https://static.docs.arm.com/ddi0602/d/ISA_A64_xml_futureA-2019-12_OPT.pdf
>
> [2] Devel tree: https://github.com/rth7680/qemu/tree/tgt-arm-sve-2
>
> Based-on: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=163610
> ("target/arm: sve load/store improvements")
>
> Based-on: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=164500
> ("target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA")
>
> Based-on: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=164048
> ("target/arm: Implement ARMv8.5-MemTag, system mode")
>
> Richard Henderson (31):
> target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
> target/arm: Implement SVE2 Integer Multiply - Unpredicated
> target/arm: Implement SVE2 integer pairwise add and accumulate long
> target/arm: Remove fp_status from helper_{recpe,rsqrte}_u32
> target/arm: Implement SVE2 integer unary operations (predicated)
> target/arm: Split out saturating/rounding shifts from neon
> target/arm: Implement SVE2 saturating/rounding bitwise shift left
> (predicated)
> target/arm: Implement SVE2 integer halving add/subtract (predicated)
> target/arm: Implement SVE2 integer pairwise arithmetic
> target/arm: Implement SVE2 saturating add/subtract (predicated)
> target/arm: Implement SVE2 integer add/subtract long
> target/arm: Implement SVE2 integer add/subtract interleaved long
> target/arm: Implement SVE2 integer add/subtract wide
> target/arm: Implement SVE2 integer multiply long
> target/arm: Implement PMULLB and PMULLT
> target/arm: Tidy SVE tszimm shift formats
> target/arm: Implement SVE2 bitwise shift left long
> target/arm: Implement SVE2 bitwise exclusive-or interleaved
> target/arm: Implement SVE2 bitwise permute
> target/arm: Implement SVE2 complex integer add
> target/arm: Implement SVE2 integer absolute difference and accumulate
> long
> target/arm: Implement SVE2 integer add/subtract long with carry
> target/arm: Create arm_gen_gvec_[us]sra
> target/arm: Create arm_gen_gvec_{u,s}{rshr,rsra}
> target/arm: Implement SVE2 bitwise shift right and accumulate
> target/arm: Create arm_gen_gvec_{sri,sli}
> target/arm: Tidy handle_vec_simd_shri
> target/arm: Implement SVE2 bitwise shift and insert
> target/arm: Vectorize SABD/UABD
> target/arm: Vectorize SABA/UABA
> target/arm: Implement SVE2 integer absolute difference and accumulate
>
> target/arm/cpu.h | 31 ++
> target/arm/helper-sve.h | 345 +++++++++++++++++
> target/arm/helper.h | 81 +++-
> target/arm/translate-a64.h | 9 +
> target/arm/translate.h | 24 +-
> target/arm/vec_internal.h | 161 ++++++++
> target/arm/sve.decode | 217 ++++++++++-
> target/arm/helper.c | 3 +-
> target/arm/kvm64.c | 2 +
> target/arm/neon_helper.c | 515 ++++---------------------
> target/arm/sve_helper.c | 757 ++++++++++++++++++++++++++++++++++---
> target/arm/translate-a64.c | 557 +++++++++++++++++++++++----
> target/arm/translate-sve.c | 557 +++++++++++++++++++++++++++
> target/arm/translate.c | 626 ++++++++++++++++++++++--------
> target/arm/vec_helper.c | 411 ++++++++++++++++++++
> target/arm/vfp_helper.c | 4 +-
> 16 files changed, 3532 insertions(+), 768 deletions(-)
> create mode 100644 target/arm/vec_internal.h
>
next prev parent reply other threads:[~2020-04-22 3:07 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-26 23:08 [PATCH for-5.1 00/31] target/arm: SVE2, part 1 Richard Henderson
2020-03-26 23:08 ` [PATCH 01/31] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 Richard Henderson
2020-04-11 18:45 ` Alex Bennée
2020-03-26 23:08 ` [PATCH 02/31] target/arm: Implement SVE2 Integer Multiply - Unpredicated Richard Henderson
2020-03-26 23:08 ` [PATCH 03/31] target/arm: Implement SVE2 integer pairwise add and accumulate long Richard Henderson
2020-03-26 23:08 ` [PATCH 04/31] target/arm: Remove fp_status from helper_{recpe, rsqrte}_u32 Richard Henderson
2020-03-26 23:08 ` [PATCH 05/31] target/arm: Implement SVE2 integer unary operations (predicated) Richard Henderson
2020-03-26 23:08 ` [PATCH 06/31] target/arm: Split out saturating/rounding shifts from neon Richard Henderson
2020-03-26 23:08 ` [PATCH 07/31] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) Richard Henderson
2020-03-26 23:08 ` [PATCH 08/31] target/arm: Implement SVE2 integer halving add/subtract (predicated) Richard Henderson
2020-03-26 23:08 ` [PATCH 09/31] target/arm: Implement SVE2 integer pairwise arithmetic Richard Henderson
2020-04-13 16:02 ` Laurent Desnogues
2020-03-26 23:08 ` [PATCH 10/31] target/arm: Implement SVE2 saturating add/subtract (predicated) Richard Henderson
2020-03-26 23:08 ` [PATCH 11/31] target/arm: Implement SVE2 integer add/subtract long Richard Henderson
2020-04-13 16:09 ` Laurent Desnogues
2020-03-26 23:08 ` [PATCH 12/31] target/arm: Implement SVE2 integer add/subtract interleaved long Richard Henderson
2020-03-26 23:08 ` [PATCH 13/31] target/arm: Implement SVE2 integer add/subtract wide Richard Henderson
2020-04-13 16:11 ` Laurent Desnogues
2020-03-26 23:08 ` [PATCH 14/31] target/arm: Implement SVE2 integer multiply long Richard Henderson
2020-03-26 23:08 ` [PATCH 15/31] target/arm: Implement PMULLB and PMULLT Richard Henderson
2020-03-26 23:08 ` [PATCH 16/31] target/arm: Tidy SVE tszimm shift formats Richard Henderson
2020-03-26 23:08 ` [PATCH 17/31] target/arm: Implement SVE2 bitwise shift left long Richard Henderson
2020-03-26 23:08 ` [PATCH 18/31] target/arm: Implement SVE2 bitwise exclusive-or interleaved Richard Henderson
2020-03-26 23:08 ` [PATCH 19/31] target/arm: Implement SVE2 bitwise permute Richard Henderson
2020-03-26 23:08 ` [PATCH 20/31] target/arm: Implement SVE2 complex integer add Richard Henderson
2020-04-13 16:20 ` Laurent Desnogues
2020-03-26 23:08 ` [PATCH 21/31] target/arm: Implement SVE2 integer absolute difference and accumulate long Richard Henderson
2020-04-13 16:15 ` Laurent Desnogues
2020-04-13 23:19 ` Richard Henderson
2020-04-14 7:04 ` Laurent Desnogues
2020-03-26 23:08 ` [PATCH 22/31] target/arm: Implement SVE2 integer add/subtract long with carry Richard Henderson
2020-04-13 16:18 ` Laurent Desnogues
2020-03-26 23:08 ` [PATCH 23/31] target/arm: Create arm_gen_gvec_[us]sra Richard Henderson
2020-03-26 23:08 ` [PATCH 24/31] target/arm: Create arm_gen_gvec_{u,s}{rshr,rsra} Richard Henderson
2020-03-26 23:08 ` [PATCH 25/31] target/arm: Implement SVE2 bitwise shift right and accumulate Richard Henderson
2020-03-26 23:08 ` [PATCH 26/31] target/arm: Create arm_gen_gvec_{sri,sli} Richard Henderson
2020-03-26 23:08 ` [PATCH 27/31] target/arm: Tidy handle_vec_simd_shri Richard Henderson
2020-03-26 23:08 ` [PATCH 28/31] target/arm: Implement SVE2 bitwise shift and insert Richard Henderson
2020-03-26 23:08 ` [PATCH 29/31] target/arm: Vectorize SABD/UABD Richard Henderson
2020-03-26 23:08 ` [PATCH 30/31] target/arm: Vectorize SABA/UABA Richard Henderson
2020-03-26 23:08 ` [PATCH 31/31] target/arm: Implement SVE2 integer absolute difference and accumulate Richard Henderson
2020-04-01 21:17 ` [PATCH for-5.1 00/31] target/arm: SVE2, part 1 Ana Pazos
2020-04-22 2:51 ` LIU Zhiwei [this message]
2020-04-22 2:55 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=eb7eea48-ecb8-f64d-83cd-66463a61d5a6@163.com \
--to=liuzwnan@163.com \
--cc=apazos@quicinc.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=rajav@quicinc.com \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).