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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id t15-20020a63460f000000b005dccf9e3b74sm7575534pga.92.2024.03.04.09.02.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Mar 2024 09:02:46 -0800 (PST) Message-ID: Date: Mon, 4 Mar 2024 07:02:43 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/8] target/arm: use FIELD macro for CNTHCTL bit definitions Content-Language: en-US To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Jean-Philippe Brucker References: <20240301183219.2424889-1-peter.maydell@linaro.org> <20240301183219.2424889-4-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/4/24 03:21, Peter Maydell wrote: > On Fri, 1 Mar 2024 at 21:19, Richard Henderson > wrote: >> >> On 3/1/24 08:32, Peter Maydell wrote: >>> We prefer the FIELD macro over ad-hoc #defines for register bits; >>> switch CNTHCTL to that style before we add any more bits. >>> >>> Signed-off-by: Peter Maydell >>> --- >>> target/arm/internals.h | 19 +++++++++++++++++-- >>> target/arm/helper.c | 9 ++++----- >>> 2 files changed, 21 insertions(+), 7 deletions(-) >>> >>> diff --git a/target/arm/internals.h b/target/arm/internals.h >>> index c93acb270cc..6553e414934 100644 >>> --- a/target/arm/internals.h >>> +++ b/target/arm/internals.h >>> @@ -224,8 +224,23 @@ FIELD(VTCR, SL2, 33, 1) >>> #define HSTR_TTEE (1 << 16) >>> #define HSTR_TJDBX (1 << 17) >>> >>> -#define CNTHCTL_CNTVMASK (1 << 18) >>> -#define CNTHCTL_CNTPMASK (1 << 19) >>> +FIELD(CNTHCTL, EL0PCTEN, 0, 1) >>> +FIELD(CNTHCTL, EL0VCTEN, 1, 1) >>> +FIELD(CNTHCTL, EVNTEN, 2, 1) >>> +FIELD(CNTHCTL, EVNTDIR, 3, 1) >> ... >>> +FIELD(CNTHCTL, EL0VTEN, 8, 1) >>> +FIELD(CNTHCTL, EL0PTEN, 9, 1) >>> +FIELD(CNTHCTL, EL1PCTEN, 10, 1) >>> +FIELD(CNTHCTL, EL1PTEN, 11, 1) >> >> These bits change definition based on HCR_E2H, which I remembered when I got to patch 5, >> which adds code nearby the existing tests of these bits. >> >> It might be confusing to only provide the E2H versions, without some extra suffix? > > Yeah, bits 8..11 are RES0 if E2H is 0; bits 3 and 2 are the same; > bits 0 and 1 change (to EL1PCTEN and EL1PCEN, so bit 0 when E2H is 0 > has the same name as bit 10 when E2H is 1). > > I don't see the need to suffix the bits that are only relevant in > one context and RES0 in the other, only the ones where the bit has > the same name but a different location, or where the same bit > number has two names. So: > > +/* > + * Depending on the value of HCR_EL2.E2H, bits 0 and 1 > + * have different bit definitions, and EL1PCTEN might be > + * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to > + * disambiguate if necessary. > + */ > +FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1) > +FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1) > +FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1) > +FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1) > +FIELD(CNTHCTL, EVNTEN, 2, 1) > +FIELD(CNTHCTL, EVNTDIR, 3, 1) > +FIELD(CNTHCTL, EVNTI, 4, 4) > +FIELD(CNTHCTL, EL0VTEN, 8, 1) > +FIELD(CNTHCTL, EL0PTEN, 9, 1) > +FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1) > +FIELD(CNTHCTL, EL1PTEN, 11, 1) > +FIELD(CNTHCTL, ECV, 12, 1) > +FIELD(CNTHCTL, EL1TVT, 13, 1) > +FIELD(CNTHCTL, EL1TVCT, 14, 1) > +FIELD(CNTHCTL, EL1NVPCT, 15, 1) > +FIELD(CNTHCTL, EL1NVVCT, 16, 1) > +FIELD(CNTHCTL, EVNTIS, 17, 1) > +FIELD(CNTHCTL, CNTVMASK, 18, 1) > +FIELD(CNTHCTL, CNTPMASK, 19, 1) > > (and updating the uses in following patches as needed) ? Looks good, thanks. r~