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To: Nicholas Piggin , Chinmay Rath , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, danielhb413@gmail.com, harshpb@linux.ibm.com References: <20240423063234.76282-1-rathc@linux.ibm.com> <20240423063234.76282-7-rathc@linux.ibm.com> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/17/24 14:48, Nicholas Piggin wrote: > On Tue Apr 23, 2024 at 4:32 PM AEST, Chinmay Rath wrote: >> Moving the below instructions to decodetree specification : >> >> divd[u, e, eu][o][.] : XO-form >> mod{sd, ud} : X-form >> >> With this patch, all the fixed-point arithmetic instructions have been >> moved to decodetree. >> The changes were verified by validating that the tcg ops generated by those >> instructions remain the same, which were captured using the '-d in_asm,op' flag. >> Also, remaned do_divwe method in fixedpoint-impl.c.inc to do_dive because it is >> now used to divide doubleword operands as well, and not just words. >> >> Signed-off-by: Chinmay Rath >> Reviewed-by: Richard Henderson > > [...] > >> +static bool do_divd(DisasContext *ctx, arg_XO *a, bool sign) >> +{ >> + gen_op_arith_divd(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb], >> + sign, a->oe, a->rc); >> + return true; >> +} >> + >> +static bool do_modd(DisasContext *ctx, arg_X *a, bool sign) >> +{ >> + REQUIRE_INSNS_FLAGS2(ctx, ISA300); >> + gen_op_arith_modd(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb], >> + sign); >> + return true; >> +} >> + >> +TRANS64(DIVD, do_divd, true); >> +TRANS64(DIVDU, do_divd, false); >> +TRANS64(DIVDE, do_dive, gen_helper_DIVDE); >> +TRANS64(DIVDEU, do_dive, gen_helper_DIVDEU); >> + >> +TRANS64(MODSD, do_modd, true); >> +TRANS64(MODUD, do_modd, false); > > Sigh. I'm having to fix a bunch of these for 32-bit builds. Just > doing the #ifdef TARGET_PPC64 ... #else qemu_build_not_reached(); > thing. > > Which is quite ugly and actually prevents using some of these > macros and requires open coding (e.g., because DIVDE helper is > not declared for 32-bit in this case). Compare sparc: # define gen_helper_pdist ({ qemu_build_not_reached(); NULL; }) etc. > Maybe we should move 64-bit only instructions into their own > .decode file and not build them for 32-bit, so we don't have > to add all these dummy translate functions for them. That's another option, yes. The decodetree script will take multiple input files to produce one output, so you could separate the insns by base vs 64-bit. r~