Re: [PATCH 6/7] target/arm: Implement HCR_EL2.TID4 traps

[Richard Henderson <richard.henderson@linaro.org>]

On 10/29/22 00:40, Peter Maydell wrote:
> For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID
> registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and
> their AArch32 equivalents).  This is a subset of the registers
> trapped by HCR_EL2.TID2, which includes all of these and also the
> CTR_EL0 register.
> 
> Our implementation already uses a separate access function for
> CTR_EL0 (ctr_el0_access()), so all of the registers currently using
> access_aa64_tid2() should also be checking TID4.  Make that function
> check both TID2 and TID4, and rename it appropriately.
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
>   target/arm/helper.c | 17 +++++++++--------
>   1 file changed, 9 insertions(+), 8 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~