[Qemu-devel] [PATCH 0/6] target/mips: Misc fixes

[Qemu-devel] [PATCH 0/6] target/mips: Misc fixes

[Aleksandar Markovic]

From: Aleksandar Markovic <amarkovic@wavecomp.com>

A collection of misc fixes for MIPS.

Aleksandar Markovic (6):
  target/mips: nanoMIPS: Remove duplicate macro definitions
  target/mips: nanoMIPS: Remove an unused macro
  target/mips: nanoMIPS: Rename macros for extracting 3-bit GPR codes
  target/mips: Correct the second argument type of cpu_supports_isa()
  target/mips: Extend gen_scwp() functionality to support EVA
  disas: nanoMIPS: Amend DSP instructions related comments

 disas/nanomips.cpp      | 119 ++++++++++++++++++++++++++++++------------------
 target/mips/cpu.h       |   2 +-
 target/mips/translate.c |  49 ++++++++------------
 3 files changed, 96 insertions(+), 74 deletions(-)

-- 
2.7.4

[Qemu-devel] [PATCH 1/6] target/mips: nanoMIPS: Remove duplicate macro definitions

[Aleksandar Markovic]

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Several macros were defined twice, with identical values.
Remove duplicates.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 057aaf9..fb2c42c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -18433,16 +18433,6 @@ static inline int decode_gpr_gpr4_zero(int r)
 }
 
 
-/* extraction utilities */
-
-#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
-#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
-#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
-#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
-#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
-#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
-
-
 static void gen_adjust_sp(DisasContext *ctx, int u)
 {
     gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], u);
-- 
2.7.4

Re: [Qemu-devel] [PATCH 1/6] target/mips: nanoMIPS: Remove duplicate macro definitions

[Philippe Mathieu-Daudé]

On 1/21/19 8:08 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
> 
> Several macros were defined twice, with identical values.
> Remove duplicates.

"Previously added in 80845edf37b."

"This reverts commit 6bfa9f4c9cf24d6cfaaa227722e9cdcca1ad6fe9."

> 
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
>  target/mips/translate.c | 10 ----------
>  1 file changed, 10 deletions(-)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 057aaf9..fb2c42c 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -18433,16 +18433,6 @@ static inline int decode_gpr_gpr4_zero(int r)
>  }
>  
>  
> -/* extraction utilities */
> -
> -#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
> -#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
> -#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
> -#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
> -#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
> -#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
> -
> -
>  static void gen_adjust_sp(DisasContext *ctx, int u)
>  {
>      gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], u);
> 

[Qemu-devel] [PATCH 2/6] target/mips: nanoMIPS: Remove an unused macro

[Aleksandar Markovic]

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Remove a macro that is never used.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index fb2c42c..aad760c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -18393,7 +18393,6 @@ enum {
 
 #define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
 #define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
-#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
 #define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
 #define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
 #define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
-- 
2.7.4

Re: [Qemu-devel] [PATCH 2/6] target/mips: nanoMIPS: Remove an unused macro

[Philippe Mathieu-Daudé]

On 1/21/19 8:08 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
> 
> Remove a macro that is never used.
> 
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
>  target/mips/translate.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index fb2c42c..aad760c 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -18393,7 +18393,6 @@ enum {
>  
>  #define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
>  #define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
> -#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
>  #define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
>  #define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
>  #define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
> 

[Qemu-devel] [PATCH 3/6] target/mips: nanoMIPS: Rename macros for extracting 3-bit GPR codes

[Aleksandar Markovic]

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Rename macros for extracting 3-bit GPR codes for better consistency
with the documentation.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index aad760c..ceaa582 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -18391,9 +18391,9 @@ enum {
 
 /* extraction utilities */
 
-#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
-#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
-#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
+#define NANOMIPS_EXTRACT_RT3(op) ((op >> 7) & 0x7)
+#define NANOMIPS_EXTRACT_RS3(op) ((op >> 4) & 0x7)
+#define NANOMIPS_EXTRACT_RD3(op) ((op >> 1) & 0x7)
 #define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
 #define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
 
@@ -18490,8 +18490,8 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
 
 static void gen_pool16c_nanomips_insn(DisasContext *ctx)
 {
-    int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
-    int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+    int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
+    int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
 
     switch (extract32(ctx->opcode, 2, 2)) {
     case NM_NOT16:
@@ -21792,9 +21792,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
 static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
 {
     uint32_t op;
-    int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
-    int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
-    int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
+    int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
+    int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
+    int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
     int offset;
     int imm;
 
@@ -21957,7 +21957,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
         case NM_SB16:
             rt = decode_gpr_gpr3_src_store(
-                     NANOMIPS_EXTRACT_RD(ctx->opcode));
+                     NANOMIPS_EXTRACT_RT3(ctx->opcode));
             gen_st(ctx, OPC_SB, rt, rs, offset);
             break;
         case NM_LBU16:
@@ -21976,7 +21976,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
             break;
         case NM_SH16:
             rt = decode_gpr_gpr3_src_store(
-                     NANOMIPS_EXTRACT_RD(ctx->opcode));
+                     NANOMIPS_EXTRACT_RT3(ctx->opcode));
             gen_st(ctx, OPC_SH, rt, rs, offset);
             break;
         case NM_LHU16:
@@ -22031,14 +22031,14 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
     case NM_SW16:
         rt = decode_gpr_gpr3_src_store(
-                 NANOMIPS_EXTRACT_RD(ctx->opcode));
-        rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+                 NANOMIPS_EXTRACT_RT3(ctx->opcode));
+        rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
         offset = extract32(ctx->opcode, 0, 4) << 2;
         gen_st(ctx, OPC_SW, rt, rs, offset);
         break;
     case NM_SWGP16:
         rt = decode_gpr_gpr3_src_store(
-                 NANOMIPS_EXTRACT_RD(ctx->opcode));
+                 NANOMIPS_EXTRACT_RT3(ctx->opcode));
         offset = extract32(ctx->opcode, 0, 7) << 2;
         gen_st(ctx, OPC_SW, rt, 28, offset);
         break;
-- 
2.7.4

[Qemu-devel] [PATCH 4/6] target/mips: Correct the second argument type of cpu_supports_isa()

[Aleksandar Markovic]

From: Aleksandar Markovic <amarkovic@wavecomp.com>

"insn_flags" bitfield was expanded from 32-bit to 64-bit at one moment.
However, this was not reflected at the second argument of the function
cpu_supports_isa(). By chance, this did not create a wrong behavior,
since the second argument was always with the left-most half zero, but
it is still a bug waiting to happen. correct by changint the type of
the second argument to be 64-bit always.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/cpu.h       | 2 +-
 target/mips/translate.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 03c03fd..fd22bd5 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1011,7 +1011,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
 
 bool cpu_supports_cps_smp(const char *cpu_type);
-bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
+bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
 void cpu_set_exception_base(int vp_index, target_ulong address);
 
 /* mips_int.c */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ceaa582..b660235 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29803,7 +29803,7 @@ bool cpu_supports_cps_smp(const char *cpu_type)
     return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
 }
 
-bool cpu_supports_isa(const char *cpu_type, unsigned int isa)
+bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
 {
     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
     return (mcc->cpu_def->insn_flags & isa) != 0;
-- 
2.7.4

Re: [Qemu-devel] [PATCH 4/6] target/mips: Correct the second argument type of cpu_supports_isa()

[Philippe Mathieu-Daudé]

On 1/21/19 8:08 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
> 
> "insn_flags" bitfield was expanded from 32-bit to 64-bit at one moment.

"at one moment" -> "in f9c9cd63e3"

> However, this was not reflected at the second argument of the function
> cpu_supports_isa(). By chance, this did not create a wrong behavior,
> since the second argument was always with the left-most half zero, but
> it is still a bug waiting to happen. correct by changint the type of
> the second argument to be 64-bit always.

Oops.

> 
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
>  target/mips/cpu.h       | 2 +-
>  target/mips/translate.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 03c03fd..fd22bd5 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1011,7 +1011,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
>  #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
>  
>  bool cpu_supports_cps_smp(const char *cpu_type);
> -bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
> +bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
>  void cpu_set_exception_base(int vp_index, target_ulong address);
>  
>  /* mips_int.c */
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index ceaa582..b660235 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -29803,7 +29803,7 @@ bool cpu_supports_cps_smp(const char *cpu_type)
>      return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
>  }
>  
> -bool cpu_supports_isa(const char *cpu_type, unsigned int isa)
> +bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
>  {
>      const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
>      return (mcc->cpu_def->insn_flags & isa) != 0;
> 

[Qemu-devel] [PATCH 5/6] target/mips: Extend gen_scwp() functionality to support EVA

[Aleksandar Markovic]

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Extend gen_scwp() functionality to support EVA by adding an
additional argument, and accordingly change related invocations.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index b660235..e57b2be 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -3708,7 +3708,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
 }
 
 static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
-                    uint32_t reg1, uint32_t reg2)
+                    uint32_t reg1, uint32_t reg2, bool eva)
 {
     TCGv taddr = tcg_temp_local_new();
     TCGv lladdr = tcg_temp_local_new();
@@ -3736,7 +3736,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
 
     tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
     tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
-                               ctx->mem_idx, MO_64);
+                               eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);
     if (reg1 != 0) {
         tcg_gen_movi_tl(cpu_gpr[reg1], 1);
     }
@@ -21481,7 +21481,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                         break;
                     case NM_SCWP:
                         check_xnp(ctx);
-                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
+                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
+                                 false);
                         break;
                     }
                     break;
@@ -21585,7 +21586,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                         check_xnp(ctx);
                         check_eva(ctx);
                         check_cp0_enabled(ctx);
-                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
+                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
+                                 true);
                         break;
                     default:
                         generate_exception_end(ctx, EXCP_RI);
-- 
2.7.4

[Qemu-devel] [PATCH 6/6] disas: nanoMIPS: Amend DSP instructions related comments

[Aleksandar Markovic]

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Amend some DSP instructions related comments.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 disas/nanomips.cpp | 119 +++++++++++++++++++++++++++++++++--------------------
 1 file changed, 75 insertions(+), 44 deletions(-)

diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
index 17f4c22..f90f1a9 100644
--- a/disas/nanomips.cpp
+++ b/disas/nanomips.cpp
@@ -1836,7 +1836,8 @@ std::string NMD::ABS_S(uint64 instruction)
 
 
 /*
- * ABSQ_S.PH rt, rs - Find Absolute Value of Two Fractional Halfwords
+ * [DSP] ABSQ_S.PH rt, rs - Find absolute value of two fractional halfwords
+ *         with 16-bit saturation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -1857,7 +1858,8 @@ std::string NMD::ABSQ_S_PH(uint64 instruction)
 
 
 /*
- * ABSQ_S.QB rt, rs - Find Absolute Value of Four Fractional Byte Values
+ * [DSP] ABSQ_S.QB rt, rs - Find absolute value of four fractional byte values
+ *         with 8-bit saturation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -1878,7 +1880,8 @@ std::string NMD::ABSQ_S_QB(uint64 instruction)
 
 
 /*
- *
+ * [DSP] ABSQ_S.W rt, rs - Find absolute value of fractional word with 32-bit
+ *         saturation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -2233,7 +2236,7 @@ std::string NMD::ADDIUPC_48_(uint64 instruction)
 
 
 /*
- * ADDQ.PH rd, rt, rs - Add Fractional Halfword Vectors
+ * [DSP] ADDQ.PH rd, rt, rs - Add fractional halfword vectors
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -2257,7 +2260,8 @@ std::string NMD::ADDQ_PH(uint64 instruction)
 
 
 /*
- * ADDQ_S.PH rd, rt, rs - Add Fractional Halfword Vectors
+ * [DSP] ADDQ_S.PH rd, rt, rs - Add fractional halfword vectors with 16-bit
+ *         saturation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -2281,7 +2285,7 @@ std::string NMD::ADDQ_S_PH(uint64 instruction)
 
 
 /*
- * ADDQ_S.W rd, rt, rs - Add Fractional Words
+ * [DSP] ADDQ_S.W rd, rt, rs - Add fractional words with 32-bit saturation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -2305,8 +2309,8 @@ std::string NMD::ADDQ_S_W(uint64 instruction)
 
 
 /*
- * ADDQH.PH rd, rt, rs - Add Fractional Halfword Vectors And Shift Right
- *                       to Halve Results
+ * [DSP] ADDQH.PH rd, rt, rs - Add fractional halfword vectors and shift
+ *         right to halve results
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -2330,8 +2334,8 @@ std::string NMD::ADDQH_PH(uint64 instruction)
 
 
 /*
- * ADDQH_R.PH rd, rt, rs - Add Fractional Halfword Vectors And Shift Right
- *                         to Halve Results
+ * [DSP] ADDQH_R.PH rd, rt, rs - Add fractional halfword vectors and shift
+ *         right to halve results with rounding
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -2355,7 +2359,8 @@ std::string NMD::ADDQH_R_PH(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] ADDQH_R.W rd, rt, rs - Add fractional words and shift right to halve
+ *         results with rounding
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -2379,7 +2384,8 @@ std::string NMD::ADDQH_R_W(uint64 instruction)
 
 
 /*
- * ADDQH.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] ADDQH.W rd, rt, rs - Add fractional words and shift right to halve
+ *         results
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -2403,7 +2409,7 @@ std::string NMD::ADDQH_W(uint64 instruction)
 
 
 /*
- * ADDSC rd, rt, rs - Add Signed Word and Set Carry Bit
+ * [DSP] ADDSC rd, rt, rs - Add two signed words and set carry bit
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -2496,7 +2502,7 @@ std::string NMD::ADDU_4X4_(uint64 instruction)
 
 
 /*
- * ADDU.PH rd, rt, rs - Unsigned Add Integer Halfwords
+ * [DSP] ADDU.PH rd, rt, rs - Add two pairs of unsigned halfwords
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -2544,7 +2550,8 @@ std::string NMD::ADDU_QB(uint64 instruction)
 
 
 /*
- * ADDU_S.PH rd, rt, rs - Unsigned Add Integer Halfwords
+ * [DSP] ADDU_S.PH rd, rt, rs - Add two pairs of unsigned halfwords with 16-bit
+ *         saturation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -7848,7 +7855,7 @@ std::string NMD::INS(uint64 instruction)
 
 
 /*
- *
+ * [DSP] INSV - Insert bit field variable
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -9698,7 +9705,8 @@ std::string NMD::LWXS_32_(uint64 instruction)
 
 
 /*
- *
+ * [DSP] MADD ac, rs, rt - Multiply two words and add to the specified
+ *         accumulator
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -9770,7 +9778,8 @@ std::string NMD::MADDF_S(uint64 instruction)
 
 
 /*
- *
+ * [DSP] MADDU ac, rs, rt - Multiply two unsigned words and add to the
+ *         specified accumulator
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -9794,7 +9803,8 @@ std::string NMD::MADDU_DSP_(uint64 instruction)
 
 
 /*
- *
+ * [DSP] MAQ_S.W.PHL ac, rs, rt - Multiply the left-most single vector
+ *         fractional halfword elements with accumulation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -9818,7 +9828,8 @@ std::string NMD::MAQ_S_W_PHL(uint64 instruction)
 
 
 /*
- *
+ * [DSP] MAQ_S.W.PHR ac, rs, rt - Multiply the right-most single vector
+ *         fractional halfword elements with accumulation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -9842,7 +9853,8 @@ std::string NMD::MAQ_S_W_PHR(uint64 instruction)
 
 
 /*
- *
+ * [DSP] MAQ_SA.W.PHL ac, rs, rt - Multiply the left-most single vector
+ *         fractional halfword elements with saturating accumulation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -9866,7 +9878,8 @@ std::string NMD::MAQ_SA_W_PHL(uint64 instruction)
 
 
 /*
- *
+ * [DSP] MAQ_SA.W.PHR ac, rs, rt - Multiply the right-most single vector
+ *         fractional halfword elements with saturating accumulation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11722,7 +11735,8 @@ std::string NMD::ORI(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PACKRL.PH rd, rs, rt - Pack a word using the right halfword from one
+ *         source register and left halfword from another source register
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11764,7 +11778,8 @@ std::string NMD::PAUSE(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PICK.PH rd, rs, rt - Pick a vector of halfwords based on condition
+ *         code bits
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11788,7 +11803,8 @@ std::string NMD::PICK_PH(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PICK.QB rd, rs, rt - Pick a vector of byte values based on condition
+ *         code bits
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11812,7 +11828,8 @@ std::string NMD::PICK_QB(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PRECEQ.W.PHL rt, rs - Expand the precision of the left-most element
+ *         of a paired halfword
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11834,7 +11851,8 @@ std::string NMD::PRECEQ_W_PHL(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PRECEQ.W.PHR rt, rs - Expand the precision of the right-most element
+ *         of a paired halfword
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11856,7 +11874,8 @@ std::string NMD::PRECEQ_W_PHR(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PRECEQU.PH.QBLA rt, rs - Expand the precision of the two
+ *         left-alternate elements of a quad byte vector
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11878,7 +11897,8 @@ std::string NMD::PRECEQU_PH_QBLA(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PRECEQU.PH.QBL rt, rs - Expand the precision of the two left-most
+ *         elements of a quad byte vector
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11900,7 +11920,8 @@ std::string NMD::PRECEQU_PH_QBL(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PRECEQU.PH.QBRA rt, rs - Expand the precision of the two
+ *         right-alternate elements of a quad byte vector
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11922,7 +11943,8 @@ std::string NMD::PRECEQU_PH_QBRA(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PRECEQU.PH.QBR rt, rs - Expand the precision of the two right-most
+ *         elements of a quad byte vector
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11944,7 +11966,9 @@ std::string NMD::PRECEQU_PH_QBR(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PRECEU.PH.QBLA rt, rs - Expand the precision of the two
+ *         left-alternate elements of a quad byte vector to four unsigned
+ *         halfwords
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11966,7 +11990,8 @@ std::string NMD::PRECEU_PH_QBLA(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PRECEU.PH.QBL rt, rs - Expand the precision of the two left-most
+ *         elements of a quad byte vector to form unsigned halfwords
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -11988,7 +12013,9 @@ std::string NMD::PRECEU_PH_QBL(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PRECEU.PH.QBRA rt, rs - Expand the precision of the two
+ *         right-alternate elements of a quad byte vector to form four
+ *         unsigned halfwords
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -12010,7 +12037,8 @@ std::string NMD::PRECEU_PH_QBRA(uint64 instruction)
 
 
 /*
- * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
+ * [DSP] PRECEU.PH.QBR rt, rs - Expand the precision of the two right-most
+ *         elements of a quad byte vector to form unsigned halfwords
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -15202,7 +15230,7 @@ std::string NMD::SUBU_32_(uint64 instruction)
 
 
 /*
- * SUBU.PH rd, rs, rt - Subtract Unsigned Integer Halfwords
+ * [DSP] SUBU.PH rd, rs, rt - Subtract unsigned unsigned halfwords
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -15226,7 +15254,7 @@ std::string NMD::SUBU_PH(uint64 instruction)
 
 
 /*
- * SUBU.QB rd, rs, rt - Subtract Unsigned Quad Byte Vector
+ * [DSP] SUBU.QB rd, rs, rt - Subtract unsigned quad byte vectors
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -15250,7 +15278,8 @@ std::string NMD::SUBU_QB(uint64 instruction)
 
 
 /*
- * SUBU_S.PH rd, rs, rt - Subtract Unsigned Integer Halfwords (saturating)
+ * [DSP] SUBU_S.PH rd, rs, rt - Subtract unsigned unsigned halfwords with
+ *         8-bit saturation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -15274,7 +15303,8 @@ std::string NMD::SUBU_S_PH(uint64 instruction)
 
 
 /*
- * SUBU_S.QB rd, rs, rt - Subtract Unsigned Quad Byte Vector (saturating)
+ * [DSP] SUBU_S.QB rd, rs, rt - Subtract unsigned quad byte vectors with
+ *         8-bit saturation
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -15298,8 +15328,8 @@ std::string NMD::SUBU_S_QB(uint64 instruction)
 
 
 /*
- * SUBUH.QB rd, rs, rt - Subtract Unsigned Bytes And Right Shift to Halve
- *                         Results
+ * [DSP] SUBUH.QB rd, rs, rt - Subtract unsigned bytes and right shift
+ *         to halve results
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -15323,8 +15353,8 @@ std::string NMD::SUBUH_QB(uint64 instruction)
 
 
 /*
- * SUBUH_R.QB rd, rs, rt - Subtract Unsigned Bytes And Right Shift to Halve
- *                           Results (rounding)
+ * [DSP] SUBUH_R.QB rd, rs, rt - Subtract unsigned bytes and right shift
+ *         to halve results with rounding
  *
  *   3         2         1
  *  10987654321098765432109876543210
@@ -16412,7 +16442,8 @@ std::string NMD::WAIT(uint64 instruction)
 
 
 /*
- * WRDSP rt, mask - Write Fields to DSPControl Register from a GPR
+ * [DSP] WRDSP rt, mask - Write selected fields from a GPR to the DSPControl
+ *         register
  *
  *   3         2         1
  *  10987654321098765432109876543210
-- 
2.7.4