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From: Richard Henderson <richard.henderson@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH for-9.1 04/19] target/i386: do not use s->tmp0 and s->tmp4 to compute flags
Date: Tue, 9 Apr 2024 20:34:52 -1000	[thread overview]
Message-ID: <ec63bef5-780e-44d0-8979-a31f7b54b07f@linaro.org> (raw)
In-Reply-To: <20240409164323.776660-5-pbonzini@redhat.com>

On 4/9/24 06:43, Paolo Bonzini wrote:
> Create a new temporary whenever flags have to use one, instead of using
> s->tmp0 or s->tmp4.  NULL can now be passed as the scratch register
> to gen_prepare_*.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>   target/i386/tcg/translate.c | 54 +++++++++++++++++++++----------------
>   1 file changed, 31 insertions(+), 23 deletions(-)
> 
> diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
> index 197cccb6c96..debc1b27283 100644
> --- a/target/i386/tcg/translate.c
> +++ b/target/i386/tcg/translate.c
> @@ -947,9 +947,9 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
>       case CC_OP_SUBB ... CC_OP_SUBQ:
>           /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
>           size = s->cc_op - CC_OP_SUBB;
> -        t1 = gen_ext_tl(s->tmp0, cpu_cc_src, size, false);
> -        /* If no temporary was used, be careful not to alias t1 and t0.  */
> -        t0 = t1 == cpu_cc_src ? s->tmp0 : reg;
> +        /* Be careful not to alias t1 and t0.  */
> +        t1 = gen_ext_tl(NULL, cpu_cc_src, size, false);
> +        t0 = (reg == t1 || !reg) ? tcg_temp_new() : reg;
>           tcg_gen_mov_tl(t0, s->cc_srcT);
>           gen_extu(size, t0);

The tcg_temp_new, mov, and extu can be had with gen_ext_tl...

>           goto add_sub;
> @@ -957,8 +957,9 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
>       case CC_OP_ADDB ... CC_OP_ADDQ:
>           /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
>           size = s->cc_op - CC_OP_ADDB;
> -        t1 = gen_ext_tl(s->tmp0, cpu_cc_src, size, false);
> -        t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
> +        /* Be careful not to alias t1 and t0.  */
> +        t1 = gen_ext_tl(NULL, cpu_cc_src, size, false);
> +        t0 = gen_ext_tl(reg == t1 ? NULL : reg, cpu_cc_dst, size, false);

... like this.

It would be helpful to update the function comments (nothing is 'compute ... to reg' in 
these functions).  Future cleanup, perhaps rename 'reg' to 'scratch', or remove the 
argument entirely where applicable.

> @@ -1109,11 +1113,13 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
>           size = s->cc_op - CC_OP_SUBB;
>           switch (jcc_op) {
>           case JCC_BE:
> -            tcg_gen_mov_tl(s->tmp4, s->cc_srcT);
> -            gen_extu(size, s->tmp4);
> -            t0 = gen_ext_tl(s->tmp0, cpu_cc_src, size, false);
> -            cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = s->tmp4,
> -                               .reg2 = t0, .use_reg2 = true };
> +            /* Be careful not to alias t1 and t0.  */
> +            t1 = gen_ext_tl(NULL, cpu_cc_src, size, false);
> +            t0 = (reg == t1 || !reg) ? tcg_temp_new() : reg;
> +            tcg_gen_mov_tl(t0, s->cc_srcT);
> +            gen_extu(size, t0);

gen_ext_tl

> +            cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = t0,
> +                               .reg2 = t1, .use_reg2 = true };
>               break;
>   
>           case JCC_L:
> @@ -1122,11 +1128,13 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
>           case JCC_LE:
>               cond = TCG_COND_LE;
>           fast_jcc_l:
> -            tcg_gen_mov_tl(s->tmp4, s->cc_srcT);
> -            gen_exts(size, s->tmp4);
> -            t0 = gen_ext_tl(s->tmp0, cpu_cc_src, size, true);
> -            cc = (CCPrepare) { .cond = cond, .reg = s->tmp4,
> -                               .reg2 = t0, .use_reg2 = true };
> +            /* Be careful not to alias t1 and t0.  */
> +            t1 = gen_ext_tl(NULL, cpu_cc_src, size, true);
> +            t0 = (reg == t1 || !reg) ? tcg_temp_new() : reg;
> +            tcg_gen_mov_tl(t0, s->cc_srcT);
> +            gen_exts(size, t0);

gen_ext_tl

With that,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


  reply	other threads:[~2024-04-10  6:35 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-09 16:43 [PATCH for-9.1 00/19] target/i386: convert 1-byte opcodes to new decoder Paolo Bonzini
2024-04-09 16:43 ` [PATCH for-9.1 01/19] target/i386: use TSTEQ/TSTNE to test low bits Paolo Bonzini
2024-04-09 16:43 ` [PATCH for-9.1 02/19] target/i386: use TSTEQ/TSTNE to check flags Paolo Bonzini
2024-04-09 16:43 ` [PATCH for-9.1 03/19] target/i386: remove mask from CCPrepare Paolo Bonzini
2024-04-09 17:23   ` Philippe Mathieu-Daudé
2024-04-09 16:43 ` [PATCH for-9.1 04/19] target/i386: do not use s->tmp0 and s->tmp4 to compute flags Paolo Bonzini
2024-04-10  6:34   ` Richard Henderson [this message]
2024-04-10 18:33     ` Paolo Bonzini
2024-04-09 16:43 ` [PATCH for-9.1 05/19] target/i386: reintroduce debugging mechanism Paolo Bonzini
2024-04-09 16:43 ` [PATCH for-9.1 06/19] target/i386: move 00-5F opcodes to new decoder Paolo Bonzini
2024-04-11  2:50   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 07/19] target/i386: extract gen_far_call/jmp, reordering temporaries Paolo Bonzini
2024-04-11  2:55   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 08/19] target/i386: allow instructions with more than one immediate Paolo Bonzini
2024-04-11  2:57   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 09/19] target/i386: move 60-BF opcodes to new decoder Paolo Bonzini
2024-04-11  4:12   ` Richard Henderson
2024-04-11 11:18     ` Paolo Bonzini
2024-04-11 14:31   ` Zhao Liu
2024-04-11 15:19   ` Zhao Liu
2024-04-11 16:43     ` Paolo Bonzini
2024-04-24 11:13     ` Paolo Bonzini
2024-04-25 15:29       ` Zhao Liu
2024-04-09 16:43 ` [PATCH for-9.1 10/19] target/i386: generalize gen_movl_seg_T0 Paolo Bonzini
2024-04-11  4:13   ` Richard Henderson
2024-04-11 14:45   ` Zhao Liu
2024-04-09 16:43 ` [PATCH for-9.1 11/19] target/i386: move C0-FF opcodes to new decoder (except for x87) Paolo Bonzini
2024-04-11  6:02   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 12/19] target/i386: merge and enlarge a few ranges for call to disas_insn_new Paolo Bonzini
2024-04-11  7:56   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 13/19] target/i386: move remaining conditional operations to new decoder Paolo Bonzini
2024-04-11  8:00   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 14/19] target/i386: move BSWAP " Paolo Bonzini
2024-04-11  8:02   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 15/19] target/i386: port extensions of one-byte opcodes " Paolo Bonzini
2024-04-11  8:08   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 16/19] target/i386: remove now-converted opcodes from old decoder Paolo Bonzini
2024-04-11  8:11   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 17/19] target/i386: decode x87 instructions in a separate function Paolo Bonzini
2024-04-09 17:20   ` Philippe Mathieu-Daudé
2024-04-11  8:16   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 18/19] target/i386: split legacy decoder into " Paolo Bonzini
2024-04-09 17:17   ` Philippe Mathieu-Daudé
2024-04-11  8:17   ` Richard Henderson
2024-04-09 16:43 ` [PATCH for-9.1 19/19] target/i386: remove duplicate prefix decoding Paolo Bonzini
2024-04-11  8:34   ` Richard Henderson

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