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Tue, 15 Apr 2025 15:04:39 -0700 (PDT) Received: from [192.168.1.87] ([38.39.164.180]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73bd22f0f28sm9444343b3a.97.2025.04.15.15.04.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Apr 2025 15:04:39 -0700 (PDT) Message-ID: Date: Tue, 15 Apr 2025 15:04:38 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 109/163] tcg/mips: Drop support for add2/sub2 Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20250415192515.232910-1-richard.henderson@linaro.org> <20250415192515.232910-110-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250415192515.232910-110-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/15/25 12:24, Richard Henderson wrote: > We now produce exactly the same code via generic expansion. > > Signed-off-by: Richard Henderson > --- > tcg/mips/tcg-target-con-set.h | 1 - > tcg/mips/tcg-target-con-str.h | 1 - > tcg/mips/tcg-target-has.h | 7 ++-- > tcg/mips/tcg-target.c.inc | 67 +---------------------------------- > 4 files changed, 3 insertions(+), 73 deletions(-) > > diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h > index 4e09c9a400..5304691dc1 100644 > --- a/tcg/mips/tcg-target-con-set.h > +++ b/tcg/mips/tcg-target-con-set.h > @@ -28,4 +28,3 @@ C_O1_I4(r, r, rz, rz, rz) > C_O1_I4(r, r, r, rz, rz) > C_O2_I1(r, r, r) > C_O2_I2(r, r, r, r) > -C_O2_I4(r, r, rz, rz, rN, rN) > diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h > index dfe2b156df..db2b225e4a 100644 > --- a/tcg/mips/tcg-target-con-str.h > +++ b/tcg/mips/tcg-target-con-str.h > @@ -17,5 +17,4 @@ REGS('r', ALL_GENERAL_REGS) > CONST('I', TCG_CT_CONST_U16) > CONST('J', TCG_CT_CONST_S16) > CONST('K', TCG_CT_CONST_P2M1) > -CONST('N', TCG_CT_CONST_N16) > CONST('W', TCG_CT_CONST_WSZ) > diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h > index 9f6fa194b9..9d86906bf3 100644 > --- a/tcg/mips/tcg-target-has.h > +++ b/tcg/mips/tcg-target-has.h > @@ -39,18 +39,15 @@ extern bool use_mips32r2_instructions; > #endif > > /* optional instructions */ > - > -#if TCG_TARGET_REG_BITS == 64 > #define TCG_TARGET_HAS_add2_i32 0 > #define TCG_TARGET_HAS_sub2_i32 0 > + > +#if TCG_TARGET_REG_BITS == 64 > #define TCG_TARGET_HAS_extr_i64_i32 1 > #define TCG_TARGET_HAS_add2_i64 0 > #define TCG_TARGET_HAS_sub2_i64 0 > #define TCG_TARGET_HAS_ext32s_i64 1 > #define TCG_TARGET_HAS_ext32u_i64 1 > -#else > -#define TCG_TARGET_HAS_add2_i32 1 > -#define TCG_TARGET_HAS_sub2_i32 1 > #endif > > /* optional instructions detected at runtime */ > diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc > index 7fae1c51e9..e69781b871 100644 > --- a/tcg/mips/tcg-target.c.inc > +++ b/tcg/mips/tcg-target.c.inc > @@ -187,8 +187,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, > #define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */ > #define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */ > #define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */ > -#define TCG_CT_CONST_N16 0x800 /* "Negatable" 16-bit: -32767 - 32767 */ > -#define TCG_CT_CONST_WSZ 0x1000 /* word size */ > +#define TCG_CT_CONST_WSZ 0x800 /* word size */ > > #define ALL_GENERAL_REGS 0xffffffffu > > @@ -207,8 +206,6 @@ static bool tcg_target_const_match(int64_t val, int ct, > return 1; > } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { > return 1; > - } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { > - return 1; > } else if ((ct & TCG_CT_CONST_P2M1) > && use_mips32r2_instructions && is_p2m1(val)) { > return 1; > @@ -765,55 +762,6 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, > return false; > } > > -static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, > - TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, > - bool cbh, bool is_sub) > -{ > - TCGReg th = TCG_TMP1; > - > - /* If we have a negative constant such that negating it would > - make the high part zero, we can (usually) eliminate one insn. */ > - if (cbl && cbh && bh == -1 && bl != 0) { > - bl = -bl; > - bh = 0; > - is_sub = !is_sub; > - } > - > - /* By operating on the high part first, we get to use the final > - carry operation to move back from the temporary. */ > - if (!cbh) { > - tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); > - } else if (bh != 0 || ah == rl) { > - tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); > - } else { > - th = ah; > - } > - > - /* Note that tcg optimization should eliminate the bl == 0 case. */ > - if (is_sub) { > - if (cbl) { > - tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); > - tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); > - } else { > - tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); > - tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); > - } > - tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); > - } else { > - if (cbl) { > - tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); > - tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); > - } else if (rl == al && rl == bl) { > - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); > - tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); > - } else { > - tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); > - tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); > - } > - tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); > - } > -} > - > #define SETCOND_INV TCG_TARGET_NB_REGS > #define SETCOND_NEZ (SETCOND_INV << 1) > #define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) > @@ -2370,15 +2318,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > } > break; > > - case INDEX_op_add2_i32: > - tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], > - const_args[4], const_args[5], false); > - break; > - case INDEX_op_sub2_i32: > - tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], > - const_args[4], const_args[5], true); > - break; > - > case INDEX_op_mb: > tcg_out_mb(s, a0); > break; > @@ -2420,10 +2359,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_st_i64: > return C_O0_I2(rz, r); > > - case INDEX_op_add2_i32: > - case INDEX_op_sub2_i32: > - return C_O2_I4(r, r, rz, rz, rN, rN); > - > case INDEX_op_qemu_ld_i32: > return C_O1_I1(r, r); > case INDEX_op_qemu_st_i32: Reviewed-by: Pierrick Bouvier