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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9ddeee5sm1685558b3a.106.2024.10.03.11.40.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Oct 2024 11:40:15 -0700 (PDT) Message-ID: Date: Thu, 3 Oct 2024 11:40:12 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/1] target/riscv: enable floating point unit To: Heinrich Schuchardt , Palmer Dabbelt , Alistair Francis , Bin Meng Cc: Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , Peter Maydell , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, kvm-riscv@lists.infradead.org References: <20240925061704.12440-1-heinrich.schuchardt@canonical.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240925061704.12440-1-heinrich.schuchardt@canonical.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/24/24 23:17, Heinrich Schuchardt wrote: > The status and mstatus CSRs contain bit field FS, which control if the > floating point unit of RISC-V hart is enabled. > > There seems to be no specification prescribing the value of the field when > entering S-mode from M-mode. But OpenSBI, as the leading SBI M-mode > firmware, has set a precedent by enabling the FPU by setting the value of > FS to 3 (dirty). > > In TCG mode, QEMU uses OpenSBI by default. Users can reasonably expect that > software running QEMU in TCG mode and in KVM mode behaves similarly. > > When QEMU in KVM mode creates a vCPU, Linux' KVM code sets FS=1 (initial) > in kvm_riscv_vcpu_fp_reset(). However, QEMU internally keeps a value of > FS=0 (off) and then synchronizes this value into KVM. Thus VS-mode software > is invoked with a disabled floating point unit. This suggests that qemu is incorrectly syncing the registers from kvm at vcpu startup. > + if (riscv_has_ext(env, RVF) || riscv_has_ext(env, RVD)) { > + env->mstatus = set_field(env->mstatus, MSTATUS_FS, env->misa_mxl); Storing misa_mxl here is wrong. That's '1' for rv32 and '2' for rv64. You want a single constant value, either '1' (initial) or '2' (clean). From the kvm source, initial seems preferable. r~